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Thu, 27 Feb 2025 01:38:25 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51R1cOYh029212 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Feb 2025 01:38:24 GMT Received: from [10.134.70.212] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Feb 2025 17:38:24 -0800 Message-ID: Date: Wed, 26 Feb 2025 17:38:23 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 11/15] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Content-Language: en-US To: Jun Nie , Rob Clark , "Abhinav Kumar" , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , References: <20250226-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v7-0-8d5f5f426eb2@linaro.org> <20250226-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v7-11-8d5f5f426eb2@linaro.org> From: Jessica Zhang In-Reply-To: <20250226-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v7-11-8d5f5f426eb2@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RWQeOJmB_1teqzxZkS3y-wgxhF4zwpMs X-Proofpoint-ORIG-GUID: RWQeOJmB_1teqzxZkS3y-wgxhF4zwpMs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_01,2025-02-26_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502270011 On 2/26/2025 4:31 AM, Jun Nie wrote: > The stage contains configuration for a mixer pair. Currently the plane > supports just one stage and 2 pipes. Quad-pipe support will require > handling 2 stages and 4 pipes at the same time. In preparation for that > add a separate define, PIPES_PER_PLANE, to denote number of pipes that > can be used by the plane. > > Signed-off-by: Jun Nie > Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++++++------- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- > 4 files changed, 11 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index 193818b02197d0737c86de7765d98732fa914e8e..81474823e6799132db71c9712046d359e3535d90 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, > if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) > bg_alpha_enable = true; > > - for (i = 0; i < PIPES_PER_STAGE; i++) { > + for (i = 0; i < PIPES_PER_PLANE; i++) { > if (!pstate->pipe[i].sspp) > continue; > set_bit(pstate->pipe[i].sspp->idx, fetch_active); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > index ba7bb05efe9b8cac01a908e53121117e130f91ec..5f010d36672cc6440c69779908b315aab285eaf0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > @@ -34,6 +34,7 @@ > #define DPU_MAX_PLANES 4 > #endif > > +#define PIPES_PER_PLANE 2 > #define PIPES_PER_STAGE 2 > #ifndef DPU_MAX_DE_CURVES > #define DPU_MAX_DE_CURVES 3 > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index ef44af5ab681c8f526333fa92531a2225983aa09..d67f2ad20b4754ca4bcb759a65a39628b7236b0f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -1078,7 +1078,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, > * resources are freed by dpu_crtc_assign_plane_resources(), > * but clean them here. > */ > - for (i = 0; i < PIPES_PER_STAGE; i++) > + for (i = 0; i < PIPES_PER_PLANE; i++) > pstate->pipe[i].sspp = NULL; > > return 0; > @@ -1129,7 +1129,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, > pipe_cfg = &pstate->pipe_cfg[0]; > r_pipe_cfg = &pstate->pipe_cfg[1]; > > - for (i = 0; i < PIPES_PER_STAGE; i++) > + for (i = 0; i < PIPES_PER_PLANE; i++) > pstate->pipe[i].sspp = NULL; > > if (!plane_state->fb) > @@ -1241,7 +1241,7 @@ void dpu_plane_flush(struct drm_plane *plane) > /* force 100% alpha */ > _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); > else { > - for (i = 0; i < PIPES_PER_STAGE; i++) > + for (i = 0; i < PIPES_PER_PLANE; i++) Hi Jun, Is there a reason why only this case was changed to PIPES_PER_PLANE but _dpu_plane_color_fill() only loops over PIPES_PER_STAGE? Similarly, I see that dpu_plane_danger_signal_ctrl() also only loops over PIPES_PER_STAGE. Thanks, Jessica Zhang > dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); > } > > @@ -1364,7 +1364,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, > &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); > > /* move the assignment here, to ease handling to another pairs later */ > - for (i = 0; i < PIPES_PER_STAGE; i++) { > + for (i = 0; i < PIPES_PER_PLANE; i++) { > if (!pstate->pipe[i].sspp) > continue; > dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], > @@ -1378,7 +1378,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, > > pstate->plane_fetch_bw = 0; > pstate->plane_clk = 0; > - for (i = 0; i < PIPES_PER_STAGE; i++) { > + for (i = 0; i < PIPES_PER_PLANE; i++) { > if (!pstate->pipe[i].sspp) > continue; > pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, > @@ -1397,7 +1397,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) > struct dpu_sw_pipe *pipe; > int i; > > - for (i = 0; i < PIPES_PER_STAGE; i += 1) { > + for (i = 0; i < PIPES_PER_PLANE; i += 1) { > pipe = &pstate->pipe[i]; > if (!pipe->sspp) > continue; > @@ -1519,7 +1519,7 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, > > drm_printf(p, "\tstage=%d\n", pstate->stage); > > - for (i = 0; i < PIPES_PER_STAGE; i++) { > + for (i = 0; i < PIPES_PER_PLANE; i++) { > pipe = &pstate->pipe[i]; > if (!pipe->sspp) > continue; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > index 052fd046e8463855b16b30389c2efc67c0c15281..18ff5ec2603ed63ce45f530ced3407d3b70c737b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > @@ -33,8 +33,8 @@ > struct dpu_plane_state { > struct drm_plane_state base; > struct msm_gem_address_space *aspace; > - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; > - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; > + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; > + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; > enum dpu_stage stage; > bool needs_qos_remap; > bool pending; > > -- > 2.34.1 >