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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab772f49361sm1279167166b.33.2025.02.12.06.55.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2025 06:55:45 -0800 (PST) Message-ID: Date: Wed, 12 Feb 2025 15:55:43 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] phy: qcom: qmp-pcie: Add PHY register retention support To: Dmitry Baryshkov , "Wenbin Yao (Consultant)" Cc: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de, abel.vesa@linaro.org, quic_qianyu@quicinc.com, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, quic_devipriy@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250211094231.1813558-1-quic_wenbyao@quicinc.com> <20250211094231.1813558-3-quic_wenbyao@quicinc.com> <7deghiadmomrz7w7vq3v7nkzq2kabq4xbhkouswjrexif7pip3@tvjlpvuulxvp> <791fa29e-a2b5-d5f6-3cbc-0f499b463262@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: LtXFC3Ocr57xobosk7yJXlJCuIeg1iAf X-Proofpoint-ORIG-GUID: LtXFC3Ocr57xobosk7yJXlJCuIeg1iAf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-12_04,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502120113 On 12.02.2025 12:07 PM, Dmitry Baryshkov wrote: > On Wed, Feb 12, 2025 at 04:31:21PM +0800, Wenbin Yao (Consultant) wrote: >> On 2/12/2025 8:13 AM, Dmitry Baryshkov wrote: >>> On Tue, Feb 11, 2025 at 05:42:31PM +0800, Wenbin Yao wrote: >>>> From: Qiang Yu >>>> >>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>>> but retains register values, which means PHY setting can be skipped during >>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>>> after that. >>>> >>>> Hence, determine whether the PHY has been enabled in bootloader by >>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>>> available, skip BCR reset and PHY register setting to establish the PCIe >>>> link with bootloader - programmed PHY settings. >>>> >>>> Signed-off-by: Qiang Yu >>>> Signed-off-by: Wenbin Yao >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 91 +++++++++++++++--------- >>>> 1 file changed, 58 insertions(+), 33 deletions(-) >>>> > >>>> @@ -4042,16 +4057,22 @@ static int qmp_pcie_power_on(struct phy *phy) >>>> unsigned int mask, val; >>>> int ret; >>>> - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], >>>> - cfg->pwrdn_ctrl); >>>> + /* >>>> + * Write CSR register for phy that doesn't support no_csr >>> what is CSR register? >> The registers of PHY. > > So 'CSR registers for phy' means 'registers of PHY for phy'? that seems > incorrect. "Control and Status Registers" Konrad