From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87148376473; Mon, 18 May 2026 02:28:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779071289; cv=none; b=Zf42e7sKsAYiOg3OFrQ15qDf2UAQGz5tvitZpp7MgBrMOXlSJEynYOYIZ0jR46OnYOc7ETI3baJMs8toQGmIkns+9zHuzr2klcShE45HjeoeivWFsqJF8owdMQ2CgBLBvePbqiWHmFT08VA6+Yh3jzkRtARe1caUliTAWDmuioo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779071289; c=relaxed/simple; bh=fxhyvREpEendYiAmr/+gqwEF8rYjHgmyjVUx6ftyuVk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=b803GaY9QzN5HIpy2zumvVVuZcEWkJ8Edkqa1X0H6GxR20+GB4UQLSNr1FgVHIvxWWTymHHP7+UnZS0h5yyr5jHSrMjw35XtuZqgXf6pNAs03F90X9FI9YvPRrC9ePy3Sp+iLbEC9nENoPkcPehCCDvgeD5K2OWJIFx45QR/z1c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=RmLFt8cf; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="RmLFt8cf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=Message-ID:Date:MIME-Version:Subject:To:From: Content-Type; bh=bzMPsyU3cTQF48tb6lC6yXy72kh3ESylZnKuLeinuiQ=; b=RmLFt8cfKGwpfgTZYDiTvbYUOu6ZQaY0k0+ZZJ0RwUI/+VM8Nndkswo/vJNqq0 4mmIe2dslN1Xiyg/u8q2n/rnwoz86j3ypEyKmz9YXPBw+DHIHr76SerhZPBT33aS +uZhuPfSt3rYtf/rb4IIivahFUAOiDo9ed4rxDhTMqz4A= Received: from [192.168.50.71] (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD35jX_eApqje7VBw--.34067S2; Mon, 18 May 2026 10:27:12 +0800 (CST) Message-ID: Date: Mon, 18 May 2026 10:27:11 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/7] PCI: cadence: HPA: Add post-link delay To: Manikandan Karunakaran Pillai , "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "mani@kernel.org" , "vigneshr@ti.com" , "jingoohan1@gmail.com" , "thomas.petazzoni@bootlin.com" , "ryder.lee@mediatek.com" , "claudiu.beznea.uj@bp.renesas.com" Cc: "robh@kernel.org" , "s-vadapalli@ti.com" , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "claudiu.beznea@tuxon.dev" , "linux-mediatek@lists.infradead.org" , "linux-renesas-soc@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20260518004246.1384532-1-18255117159@163.com> <20260518004246.1384532-4-18255117159@163.com> Content-Language: en-US From: Hans Zhang <18255117159@163.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CM-TRANSID:_____wD35jX_eApqje7VBw--.34067S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxCFyxXr4fCry7GFWDCF1fXrb_yoW5XFyxpa 4DWFWfGF18Xr45uan7Z3W5XFyavFn8A347t39a93W8XrnrCrsrtF9FgF1fuasxKFWqyr1x JF17tFsrWF1avF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07U2ZXOUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AB7H2oKeQDB1gAA3G On 5/18/26 10:16, Manikandan Karunakaran Pillai wrote: > > >> EXTERNAL MAIL >> >> >> The Cadence HPA (High Performance Architecture IP) specific link setup >> function cdns_pcie_hpa_host_link_setup() waits for the link to come up >> but does not implement the required 100 ms delay after link training >> completes for speeds > 5.0 GT/s (PCIe r6.0 sec 6.6.1). >> >> Add a call to pci_host_common_link_train_delay() immediately after the >> link is confirmed to be up, using the max_link_speed field. Also, in the >> HPA host setup function, read the device tree property "max-link-speed" >> to initialize max_link_speed if not already set by a glue driver. >> >> This ensures compliance for HPA-based platforms. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >> drivers/pci/controller/cadence/pcie-cadence-host-hpa.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c >> b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c >> index 0f540bed58e8..8ef58ed01daa 100644 >> --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c >> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c >> @@ -15,6 +15,8 @@ >> >> #include "pcie-cadence.h" >> #include "pcie-cadence-host-common.h" >> +#include "../pci-host-common.h" >> +#include "../../pci.h" >> >> static u8 bar_aperture_mask[] = { >> [RP_BAR0] = 0x3F, >> @@ -304,6 +306,8 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc >> *rc) >> ret = cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); >> if (ret) >> dev_dbg(dev, "PCIe link never came up\n"); >> + else >> + pci_host_common_link_train_delay(pcie->max_link_speed); >> >> return ret; >> } >> @@ -313,6 +317,7 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) >> { >> struct device *dev = rc->pcie.dev; >> struct platform_device *pdev = to_platform_device(dev); >> + struct device_node *np = dev->of_node; >> struct pci_host_bridge *bridge; >> enum cdns_pcie_rp_bar bar; >> struct cdns_pcie *pcie; >> @@ -343,6 +348,9 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) >> rc->cfg_res = res; >> } >> >> + if (pcie->max_link_speed < 1) >> + pcie->max_link_speed = of_pci_get_max_link_speed(np); >> + > > Similar queries as for Cadence LGA controllers. Why do you need the max_link_speed check for "<1" and > What would be the consequences of not defining the max-link-speed in dts ? Hi Manikandan, It has been replied in patch 0002. Best regards, Hans > >> /* Put EROM Bar aperture to 0 */ >> cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, >> CDNS_PCIE_EROM, 0x0); >> >> -- >> 2.43.0