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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b48652aa040sm1634050866b.20.2025.10.08.05.01.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Oct 2025 05:01:08 -0700 (PDT) Message-ID: Date: Wed, 8 Oct 2025 14:01:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/17] drm/msm/adreno: Introduce A8x GPU Support To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> <20250930-kaana-gpu-support-v1-12-73530b0700ed@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250930-kaana-gpu-support-v1-12-73530b0700ed@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: MbQCWgoJ6b-p1UPc6zx9lQ_JEsr05S6l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAyNyBTYWx0ZWRfX2EISItzqgj40 OK7qMoblGGqSQxE93pBGxAjiYKClglhQ9o+Uy51Qt3wqRGL1XKDTuKe+WNWqvO88+yE+yDR+BJu utUQfwv++FpOZn8MZvuPeBLP37YGJMu8iu1hBYPy21rXk0OA9IGKx8Ws1S/dhtI6F8C5l5ccHUN h19Wl8XEAUbBq1+ciacoGppWz3JIA6cyvsGxy41FzJC/xqGEw9ahmp0t81K4cfkllA9+akvyGwa Nwptz96RTQBi26+ZIkkqiu4kq2ig9BdyGVUJpbK7ytplSyuIG19ZHGtm1linZF/uZbVRlCJnL/+ W0di7rfnUvp/id9ZF9R4KspfHOuew9XcdqMH9IltPFtLrzzZfIrFsjJxqyiUVCWYMhgBY/eBQDM LBmLwmN2Ule6KGwaPocG8t/95+tePA== X-Authority-Analysis: v=2.4 cv=Vqcuwu2n c=1 sm=1 tr=0 ts=68e65287 cx=c_pps a=R6oCqFB+Yf/t2GF8e0/dFg==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=C_0j-PAzlxBuy3Ei6pAA:9 a=QEXdDO2ut3YA:10 a=TD8TdBvy0hsOASGTdmB-:22 X-Proofpoint-ORIG-GUID: MbQCWgoJ6b-p1UPc6zx9lQ_JEsr05S6l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-08_03,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040027 On 9/30/25 7:48 AM, Akhil P Oommen wrote: > A8x is the next generation of Adreno GPUs, featuring a significant > hardware design change. A major update to the design is the introduction > of Slice architecture. Slices are sort of mini-GPUs within the GPU which > are more independent in processing Graphics and compute workloads. Also, > in addition to the BV and BR pipe we saw in A7x, CP has more concurrency > with additional pipes. > > From a software interface perspective, these changes have a significant > impact on the KMD side. First, the GPU register space has been extensively > reorganized. Second, to avoid a register space explosion caused by the > new slice architecture and additional pipes, many registers are now > virtualized, instead of duplicated as in A7x. KMD must configure an > aperture register with the appropriate slice and pipe ID before accessing > these virtualized registers. > > This patch adds only a skeleton support for the A8x family. An A8x GPU > support will be added in an upcoming patch. > > Signed-off-by: Akhil P Oommen > --- [...] > +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + u32 val; > + > + val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); > + > + if (a6xx_gpu->cached_aperture == val) > + return; > + > + gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); unless the effect is instantenous, this needs a readback [...] > +static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu) > +{ > + return ffs(a6xx_gpu->slice_mask) - 1; > +} #define instead? Perhaps also move it closer to the user > +static void a8xx_set_ubwc_config(struct msm_gpu *gpu) You modified a6xx_calc_ubwc_config() earlier in the patch is one of them unnecessary? [...] > +static int a8xx_zap_shader_init(struct msm_gpu *gpu) You can borrow this from a6xx_gpu Perhaps moving such common functions to a separate file would be even better, I glanced over the change and there is probably some potential to commonize Konrad