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Fri, 05 Apr 2024 00:02:12 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43502BC9003661 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 5 Apr 2024 00:02:11 GMT Received: from [10.71.109.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 4 Apr 2024 17:02:10 -0700 Message-ID: Date: Thu, 4 Apr 2024 17:02:09 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH] phy: qcom: qmp-combo: Fix VCO div offset on v3 Content-Language: en-US To: Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I CC: , , , Konrad Dybcio , Bjorn Andersson , , Neil Armstrong , , Douglas Anderson , Dmitry Baryshkov References: <20240404234345.1446300-1-swboyd@chromium.org> From: Abhinav Kumar In-Reply-To: <20240404234345.1446300-1-swboyd@chromium.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Q_wGZcMFoP8FLWWXYAMl7MlV2SE4NBke X-Proofpoint-GUID: Q_wGZcMFoP8FLWWXYAMl7MlV2SE4NBke X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-04_20,2024-04-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 bulkscore=0 impostorscore=0 clxscore=1011 spamscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=926 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404040171 On 4/4/2024 4:43 PM, Stephen Boyd wrote: > Commit ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to > setup clocks") changed the offset that is used to write to > DP_PHY_VCO_DIV from QSERDES_V3_DP_PHY_VCO_DIV to > QSERDES_V4_DP_PHY_VCO_DIV. Unfortunately, this offset is different > between v3 and v4 phys: > > #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 > #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 > > meaning that we write the wrong register on v3 phys now. Add another > generic register to 'regs' and use it here instead of a version specific > define to fix this. > > This was discovered after Abhinav looked over register dumps with me > from sc7180 Trogdor devices that started failing to light up the > external display with v6.6 based kernels. It turns out that some > monitors are very specific about their link clk frequency and if the > default power on reset value is still there the monitor will show a > blank screen or a garbled display. Other monitors are perfectly happy to > get a bad clock signal. > > Cc: Douglas Anderson > Cc: Abhinav Kumar > Cc: Dmitry Baryshkov > Fixes: ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup clocks") > Signed-off-by: Stephen Boyd > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > I cross-checked the foll chipsets which use qmp_v3_usb3phy_regs_layout: -> sdm845 -> sc7180 -> sm6350 All of them have VCO_DIV at offset 0x64. And, I cross-checked the foll chipsets which use qmp_v45_usb3phy_regs_layout: -> sc8180x -> x1e80100 -> sm8250 -> sm8350 All of them have VCO_DIV at offset 0x70. Now, thing look in order to me. Hence, Reviewed-by: Abhinav Kumar