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smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b="I6YvE/gY"; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17EB0606A31B; Mon, 26 Oct 2026 09:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=I6YvE/gY Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC9ED1F031E1; Mon, 26 Oct 2026 09:22:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793006548; bh=qhR5USygJ3CB78JYGZu8Bdj4Ga57gkEWi5cn82mwy+g=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=I6YvE/gYGXgvx/dS51oJ+vhNzxFT/QgIyoyGpK6mHjSAuSnuWw0cBJjHTki1SHsbF aciQZxOgZpZF8rQWeI9JGlEKFa3jS0wX62Lz8zxnwZMfhiLTSX7/AbRR36HWY0t7eO 9alwY2VThrpLH3UISHBPp1AaV8IBF+P8wwIiokDBjkjEmW5cDjyuoObmZCephYY4g3 rUZZEzGdq5+gjjr68cMHeJBQ7xsbQEQ2xdI3ikjdSdqc4/8gOKPxE/NLRUb/aL92w9 Glt7oHfgDRwKajlCm9u/oHhLlagpTuw71DMN06V1wWogpArGYgk96jL0mvRauBbBRU ZZyCdXFS6bDZA== Message-ID: Date: Mon, 26 Oct 2026 09:22:25 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] media: qcom: camss: sm8250: set the VFE AREG clock rate from the VFE To: Atanas Filipov , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: Vladimir Zapolskiy , Loic Poulain , Gjorgji Rosikopulos , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261024094027.3095475-1-atanas.filipov@oss.qualcomm.com> <20261024094027.3095475-6-atanas.filipov@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-GB Autocrypt: addr=bod@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 24/10/2026 10:40, Atanas Filipov wrote: > The SM8250 VFE AREG clock lists four rates, 100, 200, 300 and 400 MHz, > in both the VFE and the CSID resources. The VFE only enables it, as > vfe_match_clock_names() does not match the AREG clock name, so its rate > is set by the CSID, which always selects the lowest one. > > Match the VFE AREG clock in vfe_match_clock_names(), so that the VFE > selects its rate from the pixel rate of its lines like for its other > clocks, and drop its levels from the CSID resources. The AREG clocks of > VFE0 and VFE1 share the fast AHB source, which then runs at the highest > rate requested by the two VFEs. > > Signed-off-by: Atanas Filipov > --- Sets the lowest, isn't necessarily a bug. Why is 100MHz a problem and if it is, why not just fix to 400MHz ? areg is a register access / AHB clock - your worst case outcome is 'register access goes slower' - which to me accepting we don't do driver-specific clock-aggregation => raise the clock required across VFE and CSID so that nobody looses out on the bus times.. Again instead of having a driver-specific clock aggregation mechanism, if we need to solve for two siblings voting for their parent's rate - then lets do that in CCF so that every CCF consumer benefits. That's obviously a separate and potentially large series so for this specific case I'd suggest 400MHz iff a problem can be shown. --- bod