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Fri, 10 Jul 2026 06:25:41 -0700 (PDT) X-Received: by 2002:a05:6214:440a:b0:8f1:ce6c:1385 with SMTP id 6a1803df08f44-8fec6244c20mr100585036d6.4.1783689941392; Fri, 10 Jul 2026 06:25:41 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69aa6dba523sm5449418a12.0.2026.07.10.06.25.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jul 2026 06:25:40 -0700 (PDT) Message-ID: Date: Fri, 10 Jul 2026 15:25:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY To: Qiang Yu Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> <20260518-link_mode_0519-v4-9-269cd73cc5d1@oss.qualcomm.com> <6802dc29-d783-40df-bbb8-8b2dbd94be29@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEwMDEzMyBTYWx0ZWRfX0pYyFrDmcMEA 10Btdl7eG7CemWzZ3zptKTMONTVvlzCq014yqiOpJB8nXy+9Qvlj9X0ZDXCjwOub7xxaaswSxah 6tuVesr6BOfQb1j2rh4t7O0g07gToOWY4P19RUt6mbF1d4EOVcTHyZVs43hp2GqKYv8RkTgr3zj T3nsBzbLQxTnw+wIyXK/zmmPkUPOKYEw+byhRsnkff0G/bxL4T+uUBlpwK6wJPpXphl9jdwjcXa PGfpzxVAdZoJfa5NXLlsllBr8UkdzrnRqJUt1hftIm6+q7+eMxlB4ubZjqmv2vA/f1z3rwHrb9Y KyegnXZE14XLTxylZfkEKNV8fF+K3IN/GpgCNRA0/QgGjCFCCxR8aPtkicf/IY5QBCQDpPYbuYV trJtr4hFI2TUnLKs3E6wS0g8Ro446NDqJMzLauYjMuBOdIeADP9ceh4pbnTiabqPWVnKDh+eCSr gfA7in50Z0f5uKy3bdg== X-Authority-Analysis: v=2.4 cv=WpIb99fv c=1 sm=1 tr=0 ts=6a50f2d6 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=3ei8xVDPt9LJxyTjLcQA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: ehgrhyGlIO1kY3xv0HbQw5D33ynqBxB4 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEwMDEzMyBTYWx0ZWRfX0AMWlRvo5K+O /u5Emf6UwPavw3oFao/FjTzXKWn7BQmEJl3Cxxdi6LHFDVxt96TS8u7LUgeN1ascLvBaNo12/Kb Y+t7RNZ/GfpWlJFWobSZFIskl5k9phc= X-Proofpoint-ORIG-GUID: ehgrhyGlIO1kY3xv0HbQw5D33ynqBxB4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-10_03,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607100133 On 7/10/26 3:11 PM, Qiang Yu wrote: > On Fri, Jul 10, 2026 at 10:44:20AM +0200, Konrad Dybcio wrote: >> On 7/10/26 4:19 AM, Qiang Yu wrote: >>> On Mon, Jun 29, 2026 at 11:20:07AM +0200, Konrad Dybcio wrote: >>>> On 6/29/26 7:05 AM, Qiang Yu wrote: >>>>> On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote: >>>>>> On 5/19/26 7:47 AM, Qiang Yu wrote: >>>>>>> Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and >>>>>>> PCIe3b as consumers of that shared PHY provider instead of separate PHY >>>>>>> nodes. [...] >>>>>>> + linux,pci-domain = <3>; >>>>>>> + num-lanes = <8>; >>>>>> >>>>>> Is it fine to keep num-lanes 8 here even for configurations with >>>>>> bifurcated PHY? >>>>>> >>>>>> I would assume so, given essentially this is a x8 host, whose 4 >>>>>> lanes may simply be effectively NC >>>>>> >>>>> Actually, on existing platforms, the PCIe3a and PCIe3b controllers are >>>>> never enabled at the same time. When PCIe3a is exposed, it is always in an >>>>> x8 slot. But if we have a x4+x4 platform in future, we can simply override >>>>> num-lanes to 4 in the board.dts. >>>> >>>> My question is whether that will be necessary - if yes, sure, we >>>> can do it, but if not, we can conclude on this early and not have >>>> to fight over it in a couple months >>>> >>> I think we do need to override it in that case. If both PCIe3a and PCIe3b >>> are enabled in x4+x4 mode but PCIe3a keeps num-lanes = <8>, userspace >>> will see an 8-lane slot. If an x8-capable EP is connected to that slot, >>> both ends will advertise x8 support, but the link is up at x4. That looks >>> like a genuine bug from the user's point of view. >> >> Do we know what's advertised on x86 PCs with bifurcated lanes? >> > On QCB, it advertise x8. On CRD, PCIe3a is hidden. No no, I meant to ask whether we know what the userspace gets to see on e.g. an AMD system with a bifurcated slot. I would expect that LnkCap may report a different value, but not necessarily. I would assume we should probably mimic whatever that does, unless the spec takes a stance on what should be done. Konrad