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Tue, 17 Dec 2024 07:50:54 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BH7orrD021258 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 07:50:53 GMT Received: from [10.239.133.49] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 16 Dec 2024 23:50:49 -0800 Message-ID: Date: Tue, 17 Dec 2024 15:50:47 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/2] Add Qualcomm extended CTI support From: Jinlong Mao To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20240903121847.6964-1-quic_jinlmao@quicinc.com> <742d1cec-13ec-4f08-b7f3-611c6d602b3b@quicinc.com> Content-Language: en-US In-Reply-To: <742d1cec-13ec-4f08-b7f3-611c6d602b3b@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GLJg2LnoYiq9y_XL-l9hMt1WX2YF8zQO X-Proofpoint-GUID: GLJg2LnoYiq9y_XL-l9hMt1WX2YF8zQO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 phishscore=0 spamscore=0 clxscore=1011 suspectscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170063 On 2024/10/10 17:49, Jinlong Mao wrote: > > > On 2024/9/3 20:18, Mao Jinlong wrote: >> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. >> It allows a debugger to send to trigger events to a processor or to send >> a trigger event to one or more processors when a trigger event occurs on >> another processor on the same SoC, or even between SoCs. >> >> QCOM extended CTI supports up to 128 triggers. And some of the register >> offsets are changed. >> >> The commands to configure CTI triggers are the same as ARM's CTI. >> > > Hi Reviewers, > > Could you please help to provide some comments from the design point of > view for the changes ? > > The main difference of extended CTI to the normal CTI is that the > address mapping is changed and it supports a max of 128 trigger signals. > > On one soc, there will be both normal arm CTIs and QCOM extended CTIs. > > As max trigger number becomes 128. So triger registers becomes 4. > > Like CTITRIGINSTATUS  --- > CTITRIGINSTATUS_EXTENDED(n)     (0x040 + (4 > * n))  n is 0 to 4. > > Thanks > Jinlong Mao Gentle reminder for the review from the code design point of view. > >> Mao Jinlong (2): >>    dt-bindings: arm: Add Qualcomm extended CTI >>    coresight: cti: Add Qualcomm extended CTI support >> >>   .../bindings/arm/arm,coresight-cti.yaml       |  14 ++ >>   .../hwtracing/coresight/coresight-cti-core.c  |  75 +++++++---- >>   .../coresight/coresight-cti-platform.c        |  16 ++- >>   .../hwtracing/coresight/coresight-cti-sysfs.c | 124 ++++++++++++++---- >>   drivers/hwtracing/coresight/coresight-cti.h   | 123 +++++++++++------ >>   5 files changed, 253 insertions(+), 99 deletions(-) >> >