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Tue, 18 Aug 2026 09:40:12 -0700 (PDT) Message-ID: Date: Tue, 18 Aug 2026 18:40:11 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: linux-next: manual merge of the net-next tree with the net tree To: Mark Brown , David Miller , Jakub Kicinski , Paolo Abeni , Networking Cc: Ivan Vecera , Linux Kernel Mailing List , Linux Next Mailing List References: Content-Language: en-US From: Petr Oros In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/18/26 17:42, Mark Brown wrote: > Hi all, > > Today's linux-next merge of the net-next tree got a conflict in: > > drivers/dpll/dpll_netlink.c > > between commit: > > 33f016b23a219 ("dpll: fix NULL deref in dpll_device_ops() during teardown race") > > from the net tree and commit: > > 84e85c325e5ed ("dpll: use pin owner's dpll ref for pin-level attribute setting") > > from the net-next tree. > > I fixed it up (see below) and can carry the fix as necessary. This > is now fixed as far as linux-next is concerned, but any non trivial > conflicts should be mentioned to your upstream maintainer when your tree > is submitted for merging. You may also want to consider cooperating > with the maintainer of the conflicting tree to minimise any particularly > complex conflicts. Your resolution is correct, thanks for handling it. Regards, Petr > > diff --cc drivers/dpll/dpll_netlink.c > index 9e55745e33e4f,a909cd4451b00..0000000000000 > --- a/drivers/dpll/dpll_netlink.c > +++ b/drivers/dpll/dpll_netlink.c > @@@ -1109,20 -1089,8 +1108,8 @@@ dpll_pin_freq_set(struct dpll_pin *pin > return -EINVAL; > } > > - xa_for_each(&pin->dpll_refs, i, ref) { > - if (!dpll_device_registered(ref->dpll)) > - continue; > - ops = dpll_pin_ops(ref); > - if ((!ops->frequency_set || !ops->frequency_get) && > - ref->dpll->module == pin->module && > - ref->dpll->clock_id == pin->clock_id) { > - NL_SET_ERR_MSG(extack, > - "frequency set not supported by the device"); > - return -EOPNOTSUPP; > - } > - } > ref = dpll_pin_own_dpll_ref_first(pin); > - if (!ref) { > + if (!ref || !dpll_device_registered(ref->dpll)) { > NL_SET_ERR_MSG(extack, "pin owner dpll not found"); > return -ENODEV; > } > @@@ -1181,26 -1130,13 +1149,13 @@@ dpll_pin_esync_set(struct dpll_pin *pin > const struct dpll_pin_ops *ops; > struct dpll_pin_esync esync; > u64 freq = nla_get_u64(a); > + struct dpll_pin_ref *ref; > struct dpll_device *dpll; > bool supported = false; > - unsigned long i; > - int ret; > + int ret, i; > > - xa_for_each(&pin->dpll_refs, i, ref) { > - if (!dpll_device_registered(ref->dpll)) > - continue; > - ops = dpll_pin_ops(ref); > - if ((!ops->esync_set || !ops->esync_get) && > - ref->dpll->module == pin->module && > - ref->dpll->clock_id == pin->clock_id) { > - NL_SET_ERR_MSG(extack, > - "embedded sync feature is not supported by this device"); > - return -EOPNOTSUPP; > - } > - } > ref = dpll_pin_own_dpll_ref_first(pin); > - if (!ref) { > + if (!ref || !dpll_device_registered(ref->dpll)) { > NL_SET_ERR_MSG(extack, "pin owner dpll not found"); > return -ENODEV; > } > @@@ -1313,24 -1221,16 +1240,15 @@@ dpll_pin_ref_sync_state_set(struct dpll > } > if (state == old_state) > return 0; > - xa_for_each(&pin->dpll_refs, i, ref) { > - if (!dpll_device_registered(ref->dpll)) > - continue; > - ops = dpll_pin_ops(ref); > - if (!ops->ref_sync_set) > - continue; > - dpll = ref->dpll; > - ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), > - ref_sync_pin, > - dpll_pin_on_dpll_priv(dpll, > - ref_sync_pin), > - state, extack); > - if (ret) { > - failed = ref; > - NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", > - dpll->id); > - goto rollback; > - } > - > + ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), > + ref_sync_pin, > + dpll_pin_on_dpll_priv(dpll, ref_sync_pin), > + state, extack); > + if (ret) { > + NL_SET_ERR_MSG_FMT(extack, > + "reference sync set failed for dpll_id:%u", > + dpll->id); > + return ret; > } > __dpll_pin_change_ntf(pin); > > @@@ -1534,19 -1415,8 +1433,8 @@@ dpll_pin_phase_adj_set(struct dpll_pin > return -EINVAL; > } > > - xa_for_each(&pin->dpll_refs, i, ref) { > - if (!dpll_device_registered(ref->dpll)) > - continue; > - ops = dpll_pin_ops(ref); > - if ((!ops->phase_adjust_set || !ops->phase_adjust_get) && > - ref->dpll->module == pin->module && > - ref->dpll->clock_id == pin->clock_id) { > - NL_SET_ERR_MSG(extack, "phase adjust not supported"); > - return -EOPNOTSUPP; > - } > - } > ref = dpll_pin_own_dpll_ref_first(pin); > - if (!ref) { > + if (!ref || !dpll_device_registered(ref->dpll)) { > NL_SET_ERR_MSG(extack, "pin owner dpll not found"); > return -ENODEV; > }