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Tue, 07 Apr 2026 14:14:19 -0700 (PDT) X-Received: by 2002:a17:902:f78f:b0:2b2:4d78:eec2 with SMTP id d9443c01a7336-2b281821ca2mr197860515ad.18.1775596459201; Tue, 07 Apr 2026 14:14:19 -0700 (PDT) Received: from [192.168.1.8] ([106.222.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b27472d233sm186754435ad.2.2026.04.07.14.14.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Apr 2026 14:14:18 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 02:44:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 4/6] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature To: Alexander Koskovich , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Bjorn Andersson Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio References: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> <20260402-adreno-810-v2-4-ce337ca87a9e@pm.me> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260402-adreno-810-v2-4-ce337ca87a9e@pm.me> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Rr716imK c=1 sm=1 tr=0 ts=69d573ac cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=oIjhDLspr5RTlLLUpj0f1A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=bYgO6XzdekrPMLAnqt8A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDE5MyBTYWx0ZWRfX6fLI8IY09S8F YjjnsJkwsxWPmIpSHstoQKKJMpOiRcxjAJPvvPdHnBfnVjmWihvxL0a+0Pvy3SpcHIQmaC50C4o YUAk5YB9dE4S6moDfWA5e2phS/Rg2hy7IrzBTqoAs448dlPvKjGyEToro0taKbBgUHnBaYTb8RH OJIp3EOz6MpYpjJozzH0kBruQk66BG3ZYUabLsjSTFPZyzUrWa85OTJxC0osRf+6KYXLw80MdVN 9bmNVIzbkrBJuVvL4juX2RBdqx8uhOFwoB+n7/WsrbXLVTBWVsq76YLC3pfC1pqc1iJhMB2z1AR YIUNoT5YJ7bmXZw57vLTCCWdv93+zx29MDPA83YZvpgT7is3pKImbYoKvcBZAXdLmvrCuMAJU1r T0rHTlM9LgQ2undbLOxpjP6qw4j7Bqoiokgw6VMPzC8WVoLANA5OqvlspcZffa5d+I7vH2hR7uA 6Ml/j0Drmswj2LciEAw== X-Proofpoint-ORIG-GUID: lqo2UHEKBckkb8jDDdvqq6mQHe21zx_X X-Proofpoint-GUID: lqo2UHEKBckkb8jDDdvqq6mQHe21zx_X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_04,2026-04-07_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070193 On 4/3/2026 4:39 AM, Alexander Koskovich wrote: > A8XX GPUs have two sets of protect registers: 64 global slots and 16 > pipe specific slots. The last-span-unbound feature is only available > on pipe protect registers, and should always target pipe slot 15. > > This matches the downstream driver which hardcodes pipe slot 15 for > all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on > A810. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Alexander Koskovich Reviewed-by: Akhil P Oommen -Akhil > --- > drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index 8b4b022d9a6b..102d5e751536 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -252,11 +252,12 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) > } > > /* > - * Last span feature is only supported on PIPE specific register. > - * So update those here > + * Last span setting is only being applied to the last pipe specific > + * register. Hence duplicate the last span from protect reg into the > + * BR and BV protect reg pipe 15. > */ > - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); > - a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); > + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); > + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); > > a8xx_aperture_clear(gpu); > } >