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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b182e0ecd3sm1254717a91.3.2026.11.11.01.42.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Nov 2026 01:42:26 -0800 (PST) Message-ID: Date: Wed, 11 Nov 2026 17:42:23 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 6/7] arm_mpam: Add support for memory controller MSC on DT platforms To: Ping Li Cc: sdonthineni@nvidia.com, james.morse@arm.com, robh@kernel.org, ben.horgan@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261109-mpam-resctrl-dt-knp-support-v5-0-150335a79381@oss.qualcomm.com> <20261109-mpam-resctrl-dt-knp-support-v5-6-150335a79381@oss.qualcomm.com> <20261109112737.1081437-1-leeonion.muyu@gmail.com> Content-Language: en-US From: Yin Li In-Reply-To: <20261109112737.1081437-1-leeonion.muyu@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTExMDAzOCBTYWx0ZWRfX32i1GjQNIwff IevOpaREh1o8oYfmTMgTonNrpteaGgt1JsaH4cl0Nc6+UiG+3H8Qbs/Pjr8lNSs9TqL34nWIuqQ CQYXYoyjWF0ZsZcNl8oh61RK+alpxv0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTExMDAzOCBTYWx0ZWRfX3/3jmvkE0Ogg F5q9hw73ryGfkUSMewiW8UPNYRUsi/14OfEhmqrGARlHUwxe9Q7lCony9N/bgg6WXGK8T6tTf8l 5Lkyqwo3x+vXXRjDIUUFAQW7gsPZ3FOHS2yxQeJpqpqpbA6pPH6oRcAa7DIFm891Sh7iZW9MHq/ IO9PoHHw8bOEPrDMRe4UMpyCVUE/BzHPUby2L01RKrwqEyuXk1fChwXBdj7+63P5XQn/28kkURk 0qlO8IPps9eX2Hu6CWjX1BjNY1WSRflOxzXvDbLIF4I7xoSOiBn7QN/+W4vqgkTpjsh1Ove9jxX mT9aWJdOSYm/EubyvgkZ5blIUQbMMKmaPNNOHfHaZ41mQH8yIh2OuYnDnEwmeHvtu6zucJH2ORM Daro37y+x/Fh2E0pZb8bKOYNO7icWEJU35y/ZUQhb/K4U2xH2WQNz6o1oef9MT414vVg8SDNWcq IdpGrgJYIGdMGoTlN5w== X-Proofpoint-GUID: CK6Wz6DHG8TcxPll8peVs-98vNeqyx9- X-Proofpoint-ORIG-GUID: CK6Wz6DHG8TcxPll8peVs-98vNeqyx9- X-Authority-Analysis: v=2.4 cv=BpcIUoX5 c=1 sm=1 tr=0 ts=6af43884 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=pGLkceISAAAA:8 a=dT42ApTGJaDrCQAcAPEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-11_02,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611110038 On 11/9/2026 7:27 PM, Ping Li wrote: > Tested-by: Ping Li Hi Ping, Thank you for the Tested-by — it really helps move v5 forward. To help the maintainers evaluate this series more quickly, could you share some additional information about your use case? 1. Your SoC or platform name (if publicly available), or a brief description (e.g. "server SoC with an MPAM MSC on the DDR egress path"). 2. The typical workload scenario where memory bandwidth QoS is useful for you (e.g. isolating bandwidth between tenants, preventing certain workloads from saturating DDR, etc.). 3. Which specific features did you verify on v5? (MSC probe, resctrl mount, MB allocation, mbm_total_bytes monitoring, etc.) A real usage log showing the memory controller MSC working through resctrl would also be very helpful — similar to what we have for the cache MSC: ``` root@qcom-armv8a:/sys/fs/resctrl# cat schemata L2:0=fff;65536=fff;131072=fff root@qcom-armv8a:/sys/fs/resctrl# echo "L2:0=111;65536=222;131072=333" > schemata root@qcom-armv8a:/sys/fs/resctrl# cat schemata L2:0=111;65536=222;131072=333 root@qcom-armv8a:/sys/fs/resctrl# ``` This would give the maintainers a clearer picture of the real-world value of these patches and help speed up the review. Thanks, Yin -- Thx and BRs, Yin