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Mon, 09 Nov 2026 08:40:02 -0800 (PST) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49596ea5008sm11062337f8f.26.2026.11.09.08.40.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2026 08:40:02 -0800 (PST) Message-ID: Date: Mon, 9 Nov 2026 16:40:01 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites To: Leo Yan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Anshuman Khandual , Tamas Petz , Tamas Zsoldos , Suyash Mahar , Amir Ayupov References: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1@arm.com> <20261016-trbe_enable_disable_irq_handle_refactor-v2-9-3f57cf3199b1@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-9-3f57cf3199b1@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 16/10/2026 17:55, Leo Yan wrote: > TRBSR_EL1 records the status of the buffer that just stopped. Clearing > it in trbe_enable_hw() postpones cleanup until another run starts. If > AUX output cannot restart, for example when AUX space is exhausted, > that clear never executes. Clear the status in arm_trbe_disable() > after disabling TRBE instead. Why is leaving it set a problem though? That's not mentioned. Maybe there is some later patch that requires it? It seems like clearing on enable is cleaner because it only requires one call to clear, but this replaces it with two separate calls without really saying what the benefit of the extra complexity is. > > trbe_handle_overflow() can start the next run without calling > arm_trbe_disable(). Clear the stopped buffer's syndrome and status bits > while TRBE is disabled, before attempting the AUX restart. This also > leaves the status clean when the restart fails. > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-trbe.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 26e7554d6bdd31f8a55a8bc3a7b6d4c49b984b9b..dd9c9330bb0c739795f300dafc6ce34e72fbf280 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -655,7 +655,6 @@ static void trbe_enable_hw(struct trbe_buf *buf) > WARN_ON(buf->trbe_hw_base < buf->trbe_base); > WARN_ON(buf->trbe_write < buf->trbe_hw_base); > WARN_ON(buf->trbe_write >= buf->trbe_limit); > - clr_trbe_status(); > set_trbe_base_pointer(buf->trbe_hw_base); > set_trbe_write_pointer(buf->trbe_write); > > @@ -1069,6 +1068,8 @@ static int arm_trbe_disable(struct coresight_device *csdev) > return -EINVAL; > > trbe_drain_and_disable_local(cpudata); > + clr_trbe_status(); > + > buf->cpudata = NULL; > cpudata->buf = NULL; > cpudata->mode = CS_MODE_DISABLED; > @@ -1095,6 +1096,13 @@ static int trbe_handle_overflow(struct perf_output_handle *handle) > unsigned long size; > struct etm_event_data *event_data; > > + /* > + * Clear the status. No context synchronization is required here, > + * since context synchronization will be performed before TRBE is > + * re-enabled (see trbe_enable_hw()). > + */ > + clr_trbe_status(); > + > size = trbe_get_trace_size(handle, buf, true); > if (buf->snapshot) > handle->head += size; >