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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395e4af6e88sm9630681a91.9.2026.08.24.03.28.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Aug 2026 03:28:44 -0700 (PDT) Message-ID: Date: Mon, 24 Aug 2026 18:28:40 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: ipq-cmn-pll: keep the CMN block bus clocks enabled To: Mieczyslaw Nalewaj , Konrad Dybcio , Stanislaw Pal Cc: Bjorn Andersson , Stephen Boyd , Michael Turquette , Brian Masney , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260730191353.557494-1-kuncy7@gmail.com> <20260803091003.15285-1-kuncy7@gmail.com> <8af46926-fecc-4396-973e-2290ae285998@oss.qualcomm.com> <181944c2-2484-4384-9c91-45cc87f31955@oss.qualcomm.com> <8286b42e-0314-477b-ac2e-4b410a97d833@yahoo.com> Content-Language: en-US From: Jie Luo In-Reply-To: <8286b42e-0314-477b-ac2e-4b410a97d833@yahoo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=b4iCJNGx c=1 sm=1 tr=0 ts=6a8c1cde cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=CjxXgO3LAAAA:8 a=xSVpax0bZLVpcsUhXYAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA4NyBTYWx0ZWRfX22xkhpzGCtNO mak8Y44oEXF+1BRIRNunvwI/naSLZkvs2TuoEQZ/gL4h/gNRBOzsSc1enE+Dr2THXCjvy025k5+ gIZsVJ46GA1g36qNAVydgfc64Ji7GRU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA4NyBTYWx0ZWRfX6CbIJe32A21y Pc/TBFktEs6nzrEqLYYSt+uAaw+j3kpxzhvuTPTo7k2wMGxFfs6BTfxInkxxB4LW3ImBHbydZ5I JH67fARO1iVEFaWEcfJcH1DSgMjd0u34/C1zM9rBSgZte8tBPzk7NWSw2ST1GXMF9gtyAWFMwqv 2gX/hL0lu1PXsRkboqFLANMwB4XEyDZ7+HCRtrznBGIskPrGudUWyGyc3qKMjsx2JeMRW9VOmf1 EkncWS6Q7iVSpCZrjptUkaTUbENdPcNAvICiyGLhJlfoTbGecGUKPGxCqEjn+gDTlzeHV8dGq+3 R5U10lPSjXnKm5eX28Sv61pfZ9eJtwIJAiV1p/q7HjC6dS84m2r8TTNR7o3y2kYvudtLvruTm/i AbcK490MWzM3ptVIVoQaT00F9UhRcay1t+tJNcG7sdStrfYKF6VDFwyv+5UVHhxuBsjOx9FnVsD gJRlANleDkxLfM0Itjw== X-Proofpoint-ORIG-GUID: 20uFYgD3l4Ig_QKi-yaJEZ6RBE-tmP-3 X-Proofpoint-GUID: 20uFYgD3l4Ig_QKi-yaJEZ6RBE-tmP-3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_03,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240087 On 8/22/2026 7:19 PM, Mieczyslaw Nalewaj wrote: > On Thu, Aug 20, 2026 at 01:39:52PM +0800, Jie Luo wrote: >> The CMN PLL output clocks do not depend on the AHB or SYS clocks. They >> continue to operate correctly at the fixed rates even when the AHB >> and SYS clocks are disabled. > > The PLL outputs keep running, but the AHB register interface does not. > Once autosuspend gates AHB/SYS, any later register access to the CMN > block hangs the bus. That is the bug we are fixing. As far as I understand, there is no expectation that the CMN PLL registers need to be accessed after the CMN PLL driver has finished loading on IPQ5018. Could we identify which module is blocked after the CMN PLL driver probe completes? > >> On IPQ5018, the CMN PLL provides a 50 MHz output clock that is used as >> the reference clock for the connected Ethernet device. > > Correct, and that consumer is hardwired in silicon — the internal GE > PHY and uniphy blocks take proxied this clock without any Linux driver > calling clk_get() on it. Therefore no device link exists to keep the > provider active, and CCF rightfully gates the bus clocks after probe. The UNIPHY block is the consumer of this 50 MHz clock. It divides and gates the 50 MHz clock, then routes it to the connected PHY or switch on the IPQ5018 platform. Would you be able to try this approach in your code workspace? Since the UNIPHY driver is not currently available in the upstream kernel, this may be a practical way to validate whether keeping the relevant clock path active through the UNIPHY side resolves the issue. UNIPHY register offset: 0x74 Bit 1: Clock divider control 0: no divide-by-2 1: divide by 2 enabled Bit 0: Clock gate control 0: clock disabled 1: clock enabled > > Adding DT consumers would require touching PHY and datapath drivers > across multiple subsystems just to create artificial clk references. > That is not a stable material. The v4 driver fix is minimal, correct, > and self-contained. > > Reviewed-by: Mieczyslaw Nalewaj >