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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc763810asm544031166b.43.2026.02.19.01.57.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Feb 2026 01:57:31 -0800 (PST) Message-ID: Date: Thu, 19 Feb 2026 10:57:28 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths To: webgeek1234@gmail.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> <20260218-sm8550-ddr-bw-scaling-v2-3-43a2b6d47e70@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-3-43a2b6d47e70@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: nWUq7yGN17KVovNe3FBdqHSlJB27gqYN X-Authority-Analysis: v=2.4 cv=JrL8bc4C c=1 sm=1 tr=0 ts=6996de8c cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=3ZJPoGdyOF2n25YemrEA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDA5MSBTYWx0ZWRfXyGqyneosMoTC J75UE8vgZtMVe+G+QzbkGkpFg+qHAL4Y6TRiGkcrFC/CPEL5Sam3ZDbqTiiIszSdIlrM4s7EjIm JaKAtcWUFrWcB0SbRE2sJx3F23uwqRDaz8rV1WQCnqMr/0z4apiEWAOiG2gQ6wlESnHP82mAYul ElRkDAa8k1YQe2FmqAgbBCvDNfTjHmOwO3nCCHdWTA0G8CR/0EJhI5z86VeJokpLntrreW74UNx bx/g12vd6898IlOp1oXcUonQewjsg8y09VeD7WjTof/CrfjP1+aAk3vm2Jr2VFvUJhKnuVJcM92 HRgMZogHpy15IZ5ooZ78bPGEKTS2vF54lz/JQWjMFeNYgVpEdzeleqn/8uKCJobYeuYpkEsWdse LSAyBLWOWBR/lSgr+qe3mtnoviTy6h28hCUiC9lBcuECjmnP0X/xUGip3LYMbNDX2+SxESn8FJD vP+twwlV/zXcZ30N4lg== X-Proofpoint-ORIG-GUID: nWUq7yGN17KVovNe3FBdqHSlJB27gqYN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_03,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602190091 On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote: > From: Aaron Kling > > Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) > to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache > frequency by aggregating bandwidth requests of all CPU core with referenc > to the current OPP they are configured in by the LMH/EPSS hardware. > > The effect is a proper caches & DDR frequency scaling when CPU cores > changes frequency. > > The OPP tables were built using the downstream memlat ddr, llcc & l3 > tables for each cluster types with the actual EPSS cpufreq LUT tables > from running a QCS8550 device. > > Signed-off-by: Aaron Kling > --- Once squashed: Reviewed-by: Konrad Dybcio Konrad