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[146.241.241.4]) by smtp.gmail.com with ESMTPSA id w9-20020a056402070900b00525683f9b2fsm7387270edx.5.2023.08.22.04.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Aug 2023 04:12:27 -0700 (PDT) Message-ID: Subject: Re: [net PATCH V3 2/3] octeontx2-af: CN10KB: fix PFC configuration From: Paolo Abeni To: Simon Horman , Suman Ghosh Cc: sgoutham@marvell.com, gakula@marvell.com, sbhatta@marvell.com, hkelam@marvell.com, lcherian@marvell.com, jerinj@marvell.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 22 Aug 2023 13:12:26 +0200 In-Reply-To: <20230822071607.GJ2711035@kernel.org> References: <20230821052516.398572-1-sumang@marvell.com> <20230821052516.398572-3-sumang@marvell.com> <20230822071607.GJ2711035@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2023-08-22 at 09:16 +0200, Simon Horman wrote: > On Mon, Aug 21, 2023 at 10:55:15AM +0530, Suman Ghosh wrote: > > From: Hariprasad Kelam > >=20 > > The previous patch which added new CN10KB RPM block support, > > has a bug due to which PFC is not getting configured properly. > > This patch fixes the same. >=20 > Hi Suman, >=20 > I think it would be useful to describe what the bug is - it seems like an > incorrect mask in some cases - and how that might affect users. Better > still would be commands for an example usage where the problem previously > manifested. Suman, please address Simon's feedback above in the new iteration. > >=20 > > Fixes: 99c969a83d82 ("octeontx2-pf: Add egress PFC support") > > Signed-off-by: Hariprasad Kelam > > --- > > drivers/net/ethernet/marvell/octeontx2/af/rpm.c | 17 +++++++++-------- > > 1 file changed, 9 insertions(+), 8 deletions(-) > >=20 > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/= net/ethernet/marvell/octeontx2/af/rpm.c > > index b4fcb20c3f4f..af21e2030cff 100644 > > --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c > > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c > > @@ -355,8 +355,8 @@ int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_= id, u8 tx_pause, > > =20 > > void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) > > { > > + u64 cfg, pfc_class_mask_cfg; > > rpm_t *rpm =3D rpmd; > > - u64 cfg; > > =20 > > /* ALL pause frames received are completely ignored */ > > cfg =3D rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); > > @@ -380,9 +380,11 @@ void rpm_lmac_pause_frm_config(void *rpmd, int lma= c_id, bool enable) > > rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL); > > =20 > > /* Disable all PFC classes */ > > - cfg =3D rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); > > + pfc_class_mask_cfg =3D is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL : > > + RPMX_CMRX_PRT_CBFC_CTL; >=20 > Maybe it is overkill, but as this appears at least twice, > perhaps a helper would be appropriate. I think this is a matter of personal preferences (there is another similar chunk with will not fit an helper, short of implementing it with a somewhat ugly macro. So the overall code would be asymmetric),=C2=A0 I'm fine either way. Cheers, Paolo