From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755340AbeDCKzn (ORCPT ); Tue, 3 Apr 2018 06:55:43 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:11441 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752397AbeDCKzl (ORCPT ); Tue, 3 Apr 2018 06:55:41 -0400 Subject: Re: [PATCH 3/8] bindings: PCI: designware: Add support for the EP in designware driver To: Gustavo Pimentel , "bhelgaas@google.com" , "lorenzo.pieralisi@arm.com" , "Joao.Pinto@synopsys.com" , "jingoohan1@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" References: <405911c8-fffc-5bd7-76c5-f7aabde3b7bc@ti.com> <87ba8936-e870-f52b-2ff1-0aea90d0a25c@synopsys.com> CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" From: Kishon Vijay Abraham I Message-ID: Date: Tue, 3 Apr 2018 16:25:31 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <87ba8936-e870-f52b-2ff1-0aea90d0a25c@synopsys.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tuesday 03 April 2018 04:13 PM, Gustavo Pimentel wrote: > Hi Kishon, > > On 02/04/2018 06:35, Kishon Vijay Abraham I wrote: >> >> >> On Wednesday 28 March 2018 05:08 PM, Gustavo Pimentel wrote: >>> Signed-off-by: Gustavo Pimentel >> >> Please add a commit message. > > Ok. I'll add. Thanks for noticing it. > >>> --- >>> Documentation/devicetree/bindings/pci/designware-pcie.txt | 13 +++++++++++++ >>> 1 file changed, 13 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt >>> index 6300762..4bb2e08 100644 >>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt >>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt >>> @@ -3,6 +3,7 @@ >>> Required properties: >>> - compatible: >>> "snps,dw-pcie" for RC mode; >>> + "snps,dw-pcie-ep" for EP mode; >>> - reg: Should contain the configuration address space. >>> - reg-names: Must be "config" for the PCIe configuration space. >>> (The old way of getting the configuration address space from "ranges" >>> @@ -56,3 +57,15 @@ Example configuration: >>> #interrupt-cells = <1>; >>> num-lanes = <1>; >>> }; >>> +or >>> + pcie_ep: pcie_ep@dfc00000 { >>> + compatible = "snps,dw-pcie-ep"; >>> + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ >>> + <0xdfc01000 0x0001000>, /* IP registers 2 */ >> >> Doesn't this have iATU unroll space? > > I don't think EP has it, but I'm no expert on this matter. Can you provide me > some example of having iATU unroll space mapping would be useful in EP scope? I'm not sure. I thought if the dwc3 core version is 4.80, then it'll have a separate ATU space irrespective of RC mode or EP mode. Thanks Kishon