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Tue, 16 Jun 2026 04:33:20 -0700 (PDT) X-Received: by 2002:a05:620a:2729:b0:911:dfb8:37c9 with SMTP id af79cd13be357-9161bc7409cmr343124285a.3.1781609600316; Tue, 16 Jun 2026 04:33:20 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bfdb7b6e6c9sm639951166b.39.2026.06.16.04.33.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jun 2026 04:33:19 -0700 (PDT) Message-ID: Date: Tue, 16 Jun 2026 13:33:17 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/11] clk: qcom: dispcc-sm8250: Enable parents for pixel clocks To: Marek Szyprowski , Val Packett , Bjorn Andersson , Michael Turquette , Stephen Boyd , Jonathan Marek Cc: Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260312112321.370983-1-val@packett.cool> <20260312112321.370983-9-val@packett.cool> <2f5b98a4-80a6-4611-9615-ab0202a8c455@samsung.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <2f5b98a4-80a6-4611-9615-ab0202a8c455@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: DsNdpZRPd6zWCoDXYWcCE-5thNriKAV3 X-Proofpoint-ORIG-GUID: DsNdpZRPd6zWCoDXYWcCE-5thNriKAV3 X-Authority-Analysis: v=2.4 cv=I4RVgtgg c=1 sm=1 tr=0 ts=6a313481 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=iR95WtxUERvl_OCU54AA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE2MDExNyBTYWx0ZWRfX0nKL0ghtKgBy 8GRDxOf4UWSKiOuv8PcL4C7yL5Hkq1ufdywORfRfbUCk6fiZdeRajyHFeBsEPmscpTvj4+auH41 xvUhbYextBJPiOiE0yUaLHisSHJWxUY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE2MDExNyBTYWx0ZWRfX0gUPUSrUfkOu Qcfw9C+B+eHKXrUjD79ltRtnQ1jRUPMqIhhs9NQnrkwC2uIA1m0zPefqsc28j0kGYaTXL8lWn/M bZ1o/KfMMY1roBbEkFZJzlboase+zcU5Ch1lvOS3AIDC2x+lQVl+MtuA8eFdseLupl5ugseUHzF E44roSRTCloAW7OndE10lftQ2LysQWsm2DiMD2z3xWqZaABO5bnrGjzST/mfFXSXH46ZR0Wl2Yi 03/83sqfASxXQIG/6y6HRn+gJ5GqRZNSKlsq1qk1HpANm+NpiQTGxgVWYxF7eY3cjwM2A3VZeH4 HMGeGBBef7ziKs2CX+6nkkkLIXoFyH4Lv0IkvxSF6S1FUWSwCUY014RadHfvrZil0rynxo6Nic2 uKXrTmhOnjsigeqIXMSVwF82jcnr6FfiDElI4nyZw3h61Sw1RcRYk4eMF+MEYo92J5c/oR6ZRkc UUGRsiXXrGWSwnOS4cQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_03,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606160117 On 3/20/26 12:32 PM, Marek Szyprowski wrote: > Hi, > > On 12.03.2026 12:12, Val Packett wrote: >> Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent >> clocks are enabled during clock operations, preventing potential >> stability issues during display configuration. >> >> Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") >> Signed-off-by: Val Packett > > This patch landed in yesterday's linux-next as commit. In my tests I > found that it triggers the following warning on RB5 board: Hi, I was clearing out my inbox.. Is this still happening on the latest next? Konrad > > ------------[ cut here ]------------ > dsi0_phy_pll_out_dsiclk already disabled > WARNING: drivers/clk/clk.c:1188 at clk_core_disable+0x1ac/0x1bc, CPU#1: > kworker/u32:6/120 > Modules linked in: ... > CPU: 1 UID: 0 PID: 120 Comm: kworker/u32:6 Not tainted 7.0.0-rc1+ #12425 > PREEMPT > Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT) > Workqueue: events_unbound deferred_probe_work_func > pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) > pc : clk_core_disable+0x1ac/0x1bc > lr : clk_core_disable+0x1ac/0x1bc > sp : ffff800081a2b990 > ... > Call trace: >  clk_core_disable+0x1ac/0x1bc (P) >  __clk_set_parent_after+0x9c/0xf0 >  clk_core_set_parent_nolock+0x1f8/0x230 >  clk_set_parent+0x40/0x84 >  of_clk_set_defaults+0x130/0x4b8 >  platform_probe+0x38/0xac >  really_probe+0xbc/0x298 >  __driver_probe_device+0x78/0x12c >  driver_probe_device+0x40/0x164 >  __device_attach_driver+0xa4/0x148 >  bus_for_each_drv+0x80/0xdc >  __device_attach+0xa8/0x1b0 >  device_initial_probe+0x50/0x54 >  bus_probe_device+0x38/0xa8 >  deferred_probe_work_func+0x8c/0xc8 >  process_one_work+0x20c/0x78c >  worker_thread+0x244/0x388 >  kthread+0x140/0x14c >  ret_from_fork+0x10/0x20 > irq event stamp: 336832 > hardirqs last  enabled at (336831): [] > _raw_spin_unlock_irqrestore+0x74/0x78 > hardirqs last disabled at (336832): [] > clk_enable_lock+0xcc/0x110 > softirqs last  enabled at (336804): [] > handle_softirqs+0x624/0x63c > softirqs last disabled at (336793): [] > __do_softirq+0x14/0x20 > ---[ end trace 0000000000000000 ]--- > ------------[ cut here ]------------ > dsi0_phy_pll_out_dsiclk already unprepared > WARNING: drivers/clk/clk.c:1047 at clk_core_unprepare+0x1f0/0x210, > CPU#6: kworker/u32:6/120 > > It looks like a bug in the code performing the default clocks > configuration though. > >> --- >> drivers/clk/qcom/dispcc-sm8250.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c >> index cdfdb2cfb02b..e59cdadd5647 100644 >> --- a/drivers/clk/qcom/dispcc-sm8250.c >> +++ b/drivers/clk/qcom/dispcc-sm8250.c >> @@ -578,7 +578,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { >> .name = "disp_cc_mdss_pclk0_clk_src", >> .parent_data = disp_cc_parent_data_6, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), >> - .flags = CLK_SET_RATE_PARENT, >> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, >> .ops = &clk_pixel_ops, >> }, >> }; >> @@ -592,7 +592,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { >> .name = "disp_cc_mdss_pclk1_clk_src", >> .parent_data = disp_cc_parent_data_6, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), >> - .flags = CLK_SET_RATE_PARENT, >> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, >> .ops = &clk_pixel_ops, >> }, >> }; > > Best regards