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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6594a2351e6sm1991383a12.33.2026.02.05.04.03.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Feb 2026 04:03:22 -0800 (PST) Message-ID: Date: Thu, 5 Feb 2026 13:03:18 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/7] dt-bindings: clock: qcom,sm8250-videocc: account for the MX domain To: Krzysztof Kozlowski , Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Jonathan Marek , Ulf Hansson , "Rafael J. Wysocki" , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Stanimir Varbanov , Abhinav Kumar , Hans Verkuil , Stefan Schmidt , Konrad Dybcio , Bryan O'Donoghue , Dikshita Agarwal , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, Mauro Carvalho Chehab References: <20260204-iris-venus-fix-sm8250-v3-0-70fa68e57f96@oss.qualcomm.com> <20260204-iris-venus-fix-sm8250-v3-1-70fa68e57f96@oss.qualcomm.com> <20260205-abiding-beautiful-locust-6ee1b5@quoll> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260205-abiding-beautiful-locust-6ee1b5@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDA4NyBTYWx0ZWRfX9IPCurT7VKgu UQE8R6bwt88mfIP4coLybkLwkmN6o+VSStPgo/BPeXBkiFsH16rXSu5hJDwMMskZ9yPyjQEOnGc T+zzQ48XxWBNPZCui3u1ws3e/Jd17zDnJnSqwU8wBKkxkdbw96GUfMEaEquufyP0vyijHfNMJ6B f6Ul88W9bAuktgmsmUXPZrPS/vclYNRgDQunyIseNNrs0XeL5JyRyAsidXybvvQ3ueiFXi7+WBp gjL5pneAoypOmglJLri+2ePFsSnOHsaUrdlMttPehN3uiWRGeCgx1CmlvFnbKK3ROZpBR0HtJfV gfmA99IEjgpGXe50vMfhDOHOzuee4xg84EbHpGyr29Mc5lGfACUfXXSSCvLMt+42xZINir+1KmZ IZ3iXrcjL5/aILUXtvqCqKkSfGeCWl673KMYgfVW09vnFJAwDVnFUfNiDjw+naTF4S9iLmbjmZh lgZ2T/dgXBa3JbDju+w== X-Authority-Analysis: v=2.4 cv=GdcaXAXL c=1 sm=1 tr=0 ts=6984870c cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=eYRqk91NNi6RPXgtGVkA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: 15IoPzG_nQ7dacWeswiV4pocEOXuxA_d X-Proofpoint-GUID: 15IoPzG_nQ7dacWeswiV4pocEOXuxA_d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_02,2026-02-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050087 On 2/5/26 12:31 PM, Krzysztof Kozlowski wrote: > On Wed, Feb 04, 2026 at 02:59:49AM +0200, Dmitry Baryshkov wrote: >> To configure the video PLLs and enable the video GDSCs on SM8250, >> platform, the MX rail must be ON along with MMCX. Split the bindings >> file in order to provide separate file utilizing MMCX and MX power >> domains. > > ... > >> + >> +description: | >> + Qualcomm video clock control module provides the clocks, resets and power >> + domains on Qualcomm SoCs. >> + >> + See also:: > > Only one ':', please. It was a mistake to introduce :: > >> + clock-names: >> + items: >> + - const: iface >> + - const: bi_tcxo >> + - const: bi_tcxo_ao >> + >> + power-domains: >> + items: >> + - description: >> + A phandle and PM domain specifier for the MMCX power domain. >> + - description: >> + A phandle and PM domain specifier for the MX power domain. > > This is an ABI break, so please say in the commit what was not working > or why this ABI break is really justified. Currently you just give a > hint that it is needed for PLL configuration, but honestly - why would > we care to configure PLL if everything was working correct before? I fully expect it to kaboom if you turn off the display (which also holds a high vote on MMCX) Konrad