Re: Patch "riscv: topology: fix default topology reporting" has been added to the 6.0-stable tree

[<Conor.Dooley@microchip.com>]

On 16/10/2022 10:32, gregkh@linuxfoundation.org wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> This is a note to let you know that I've just added the patch titled
> 
>     riscv: topology: fix default topology reporting
> 
> to the 6.0-stable tree which can be found at:
>     http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
> 
> The filename of the patch is:
>      riscv-topology-fix-default-topology-reporting.patch
> and it can be found in the queue-6.0 subdirectory.
> 
> If you, or anyone else, feels it should not be added to the stable tree,
> please let <stable@vger.kernel.org> know about it.

Hey Greg,
This breaks the build on 6.0 (and I can only assume on the other
stable queues too).

I put:
> CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code
in the patch itself, did I specify the dependency incorrectly?

Thanks,
Conor.

> 
> 
> From fbd92809997a391f28075f1c8b5ee314c225557c Mon Sep 17 00:00:00 2001
> From: Conor Dooley <conor.dooley@microchip.com>
> Date: Fri, 15 Jul 2022 18:51:56 +0100
> Subject: riscv: topology: fix default topology reporting
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> commit fbd92809997a391f28075f1c8b5ee314c225557c upstream.
> 
> RISC-V has no sane defaults to fall back on where there is no cpu-map
> in the devicetree.
> Without sane defaults, the package, core and thread IDs are all set to
> -1. This causes user-visible inaccuracies for tools like hwloc/lstopo
> which rely on the sysfs cpu topology files to detect a system's
> topology.
> 
> On a PolarFire SoC, which should have 4 harts with a thread each,
> lstopo currently reports:
> 
> Machine (793MB total)
>   Package L#0
>     NUMANode L#0 (P#0 793MB)
>     Core L#0
>       L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
>       L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
>       L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)
>       L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)
> 
> Adding calls to store_cpu_topology() in {boot,smp} hart bringup code
> results in the correct topolgy being reported:
> 
> Machine (793MB total)
>   Package L#0
>     NUMANode L#0 (P#0 793MB)
>     L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
>     L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
>     L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
>     L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
> 
> CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code
> Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
> Reported-by: Brice Goglin <Brice.Goglin@inria.fr>
> Link: https://github.com/open-mpi/hwloc/issues/536
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> ---
>  arch/riscv/Kconfig          |    2 +-
>  arch/riscv/kernel/smpboot.c |    3 ++-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -52,7 +52,7 @@ config RISCV
>         select COMMON_CLK
>         select CPU_PM if CPU_IDLE
>         select EDAC_SUPPORT
> -       select GENERIC_ARCH_TOPOLOGY if SMP
> +       select GENERIC_ARCH_TOPOLOGY
>         select GENERIC_ATOMIC64 if !64BIT
>         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
>         select GENERIC_EARLY_IOREMAP
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -49,6 +49,7 @@ void __init smp_prepare_cpus(unsigned in
>         unsigned int curr_cpuid;
> 
>         curr_cpuid = smp_processor_id();
> +       store_cpu_topology(curr_cpuid);
>         numa_store_cpu_info(curr_cpuid);
>         numa_add_cpu(curr_cpuid);
> 
> @@ -162,9 +163,9 @@ asmlinkage __visible void smp_callin(voi
>         mmgrab(mm);
>         current->active_mm = mm;
> 
> +       store_cpu_topology(curr_cpuid);
>         notify_cpu_starting(curr_cpuid);
>         numa_add_cpu(curr_cpuid);
> -       update_siblings_masks(curr_cpuid);
>         set_cpu_online(curr_cpuid, 1);
> 
>         /*
> 
> 
> Patches currently in stable-queue which might be from conor.dooley@microchip.com are
> 
> queue-6.0/riscv-always-honor-the-config_cmdline_force-when-parsing-dtb.patch
> queue-6.0/riscv-pass-mno-relax-only-on-lld-15.0.0.patch
> queue-6.0/riscv-topology-fix-default-topology-reporting.patch
> queue-6.0/risc-v-re-enable-counter-access-from-userspace.patch