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Fri, 20 Mar 2026 23:58:33 -0700 (PDT) X-Received: by 2002:a05:6a21:99a6:b0:398:849a:847a with SMTP id adf61e73a8af0-39bcec0c6f8mr5028560637.42.1774076312974; Fri, 20 Mar 2026 23:58:32 -0700 (PDT) Received: from [192.168.29.146] ([49.43.232.136]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c743a9391b0sm3085441a12.15.2026.03.20.23.58.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Mar 2026 23:58:32 -0700 (PDT) Message-ID: Date: Sat, 21 Mar 2026 12:28:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: qcm6490-idp: Enable PCIe1 To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260212-qcm6490-idp-v1-1-80a45bd46ac5@oss.qualcomm.com> Content-Language: en-US From: Sushrut Shree Trivedi In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=aJv9aL9m c=1 sm=1 tr=0 ts=69be419a cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=RObWm1bxEibDRpuCBrDfiQ==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=ZNl6TJjcOq9ufUx7pSgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: SgAcRz7uwW7HQxtPOuMmtxoLHUAqCydN X-Proofpoint-ORIG-GUID: SgAcRz7uwW7HQxtPOuMmtxoLHUAqCydN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIxMDA1NCBTYWx0ZWRfX6iw0SPRqg2nj 6e13aWlfVIvzlXxZZV7K7vt6+OKueCjWvMPCbTd3UHzn8CroHy+j/RNyeoAmDJ6RAB+Udxnbxzy 0PI+0GLOuc+N12IhwKbWrbxROzevJsYzOEwOMIGrn+Y2doIgElwVBHCZ1+tcsrJSrXo2rsYMkCp aEvEgBlwKbvRgF833mNrYRRp9OPSet+vKmq/GzyCT4XDSxAUES7aR6gwfohyoBen6lN2T1FDyBF 3CHgib18WflcRXqWliU8aKl1jYrhDO0Zje+cZY56NQENpxTZQH9gqZ+kMEkkpJel1WqRl938OGk GzwomDosAahmVyLTRFg+1mCvdZ8GktKVYMgshZA3i1lethafZPgLFnYpNkudFEOIC8ZOgabBGUf rAYuSbHUGQ1wIK05W/sduNCMyWeh3Fk1FFCQ97zttT6cgB0RFU9vKB9Vnid6YXqj5nwOEZjDZCt PMBPUgWap9/9JQptptQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-21_02,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603210054 On 2/19/2026 7:02 PM, Bjorn Andersson wrote: > On Thu, Feb 12, 2026 at 05:36:29PM +0530, Sushrut Shree Trivedi wrote: >> Remove PCIe1 clocks from protected-list and enable PCIe1 controller >> and its corresponding PHY nodes on qcm6490-idp platform. >> > Does this mean that the firmware has changed or does it mean that the > protected-clocks list has been wrong all along? Is the remaining part > of the list correct? No, there is no change in firmware. During initial chipset bring-up, clocks related to unused peripherals are marked as protected to prevent them from being turned on by mistake. If there is a need to enable a particular peripheral later on (e.g. PCIe1 here), the respective clocks can be removed from protected list so they can be enabled by respective drivers. The remaining list contains clocks for currently unused peripherals. >> PCIe1 is used to connect NVMe based SSD's on this platform. >> > "used to connect" sounds like it's optional. If the NVMe is soldered to > the board then say that in the commit message. Ack'd > >> Signed-off-by: Sushrut Shree Trivedi >> --- >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 39 +++++++++++++++++++++++++++----- >> 1 file changed, 33 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> index 089a027c57d5..1fac051ab3e7 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> @@ -533,12 +533,7 @@ vreg_bob_3p296: bob { >> }; >> >> &gcc { >> - protected-clocks = ,, >> - , , >> - , , >> - , , >> - , , >> - , , >> + protected-clocks = , , >> ,, >> , , >> , >> @@ -615,6 +610,22 @@ &mdss_dsi_phy { >> status = "okay"; >> }; >> >> +&pcie1 { >> + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; >> + >> + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; >> + pinctrl-names = "default"; >> + >> + status = "okay"; >> +}; >> + >> +&pcie1_phy { >> + vdda-phy-supply = <&vreg_l10c_0p88>; >> + vdda-pll-supply = <&vreg_l6b_1p2>; >> + >> + status = "okay"; >> +}; >> + >> &pm7250b_gpios { >> lcd_disp_bias_en: lcd-disp-bias-en-state { >> pins = "gpio2"; >> @@ -920,6 +931,22 @@ &tlmm { >> gpio-reserved-ranges = <32 2>, /* ADSP */ >> <48 4>; /* NFC */ >> >> + pcie1_reset_n: pcie1-reset-n-state { >> + pins = "gpio2"; >> + function = "gpio"; >> + drive-strength = <16>; >> + output-low; >> + bias-disable; >> + }; > That doesn't look right. There seems to be multiple default pinctrl configurations for perst. On rb3 industrial kit we used the same output-low & bias-disable configuration while for other targets, I see we have used bias-pull-up. I feel the current config is more appropriate since it ensures the endpoint remains under reset and doesn't try to link-up with host until the controller driver initiates link training. Do you suggest a different configuration ? >> + >> + pcie1_wake_n: pcie1-wake-n-state { >> + pins = "gpio3"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + > Extra white space. Ack'd > > Thanks, > Bjorn > >> sd_cd: sd-cd-state { >> pins = "gpio91"; >> function = "gpio"; >> >> --- >> base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2 >> change-id: 20260212-qcm6490-idp-24f7b6a1812d >> >> Best regards, >> -- >> Sushrut Shree Trivedi >>