From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Masami Hiramatsu <mhiramat@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: socionext: add missing cache properties
Date: Mon, 24 Apr 2023 10:27:06 +0900 [thread overview]
Message-ID: <f9a2c0d7-a78d-9368-f9bb-e8aba11e7d81@socionext.com> (raw)
In-Reply-To: <20230421223147.115156-1-krzysztof.kozlowski@linaro.org>
Hi Krzysztof,
Thank you for your patch.
I'll take this when updating the devicetree for next.
Thank you,
On 2023/04/22 7:31, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified and cache-level properties to fix warnings like:
>
> uniphier-ld11-ref.dtb: l2-cache: 'cache-level' is a required property
> uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Please take the patch via sub-arch SoC tree.
> ---
> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 ++
> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 4 ++++
> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++
> 3 files changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> index 7bb36b071475..4680571c264d 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> @@ -52,6 +52,8 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> index 4e2171630272..335093da6573 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> @@ -86,10 +86,14 @@ cpu3: cpu@101 {
>
> a72_l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> };
>
> a53_l2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> index 38ccfb46ea42..d6e3cc6fdb25 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> @@ -83,6 +83,8 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> };
> };
>
---
Best Regards
Kunihiko Hayashi
prev parent reply other threads:[~2023-04-24 1:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 22:31 Krzysztof Kozlowski
2023-04-24 1:27 ` Kunihiko Hayashi [this message]
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