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a=WeWmnZmh0fydH62SvGsd2A==:17 a=lCpzRmAYbLLaTzLvsPZ7Mbvzbb8=:19 a=wKuvFiaSGQ0qltdbU6+NXLB8nM8=:19 a=Ol13hO9ccFRV9qXi2t6ftBPywas=:19 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=GoEa3M9JfhUA:10 a=yC-0_ovQAAAA:8 a=yPCof4ZbAAAA:8 a=PpvvzeyspNopl2-bpPQA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAxMDA3NCBTYWx0ZWRfX2i3a8nUnQ6hS lh0F9FIgtyp0193a7jcXwP5scdXqrwU+9VVZlLkUOsQfEePq07Ro4Wo7eVHpxsS4q2KfejkVrEw GrwdOjcLTEpMAbmlN08spsy8VWiM0ZSn+/C6KaEA2qpy4+DnG10uOYH6yIrtyDzvtVe4vj7vx5u EAIpy1Nt+TsTy4yddrenj+rpU5p+tseUJ8zyCgh0utXqwKpccZJx/gUUbzAX69Wijq0E8g6lyUy LvMzUyXmyd9G1WE8VUbbEeAI4miLEakzxY19TDmD3+ezTIv5OGqj7o4k1uvZ8KTSqGBSj2PY+B+ Iy84pWoHOHGwnPTNfkXX62xXPf7hVnuZEzVv3Ln8Tu7h16r17ZAFu81qAviGGeqTvZDY86pu3Jo z3vXlA5AP0MBmEodWADyq1mYQLHQvIYF3xSy7twVH1DCf0xdf9iSxOmRpXroMkTzpYTP2/ze On 01-05-2025 02:10, Prabhakar wrote: > From: Lad Prabhakar > > Add support for PLLDSI and PLLDSI divider clocks. > > Introduce the `renesas-rzv2h-dsi.h` header to centralize and share > PLLDSI-related data structures, limits, and algorithms between the RZ/V2H > CPG and DSI drivers. > > The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly > different parameter limits and omits the programmable divider present in > CPG. To ensure precise frequency calculations-especially for milliHz-level > accuracy needed by the DSI driver-the shared algorithm allows both drivers > to compute PLL parameters consistently using the same logic and input > clock. > > Co-developed-by: Fabrizio Castro > Signed-off-by: Fabrizio Castro > Signed-off-by: Lad Prabhakar Acked-by: Alok Tiwari Thanks, Alok