From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AFCE1ACECE for ; Mon, 30 Dec 2024 18:27:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735583268; cv=none; b=MPp33koY1Dj9NDthpEiS2QhmSRfQgTBs/P1wWwbTw5V7HGYzaSPUUwn4gGAjF5kbir1oZxW0ICepyo9Crdt4LIl7VB8EwbLFPJScrMDJoP7nuOrpwqteNQRIO4qnfmUM4KbQn4j0FspI0B9BkXAqU0hsYMKXTJcBwR/Sr7oTKUA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735583268; c=relaxed/simple; bh=KqK7EhrdTyWnmu/XBKWNIqYmlq9r00DoSE4UPt4uyrA=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=YpcsLTuPcpoVrhahUs/sFk/FRh5CGzX50RmzjAq15P4uC2jAqibAEKK6un75KvQKx0/TRZuhBXsM85dq2Y5V0DaSr4GbphD67tfgpP22688msOES7weEQSLZrte0kUcmrCvLIsFGV+js8AzKDjiJrjEvg+OsRWtQ9kavFPNous4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSKUP-000000000Mg-1WXb; Mon, 30 Dec 2024 13:27:41 -0500 Message-ID: Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions From: Rik van Riel To: Nadav Amit Cc: the arch/x86 maintainers , Linux Kernel Mailing List , kernel-team@meta.com, Dave Hansen , luto@kernel.org, peterz@infradead.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Andrew Morton , zhengqi.arch@bytedance.com, "open list:MEMORY MANAGEMENT" Date: Mon, 30 Dec 2024 13:27:40 -0500 In-Reply-To: <40C8627F-0B0B-4F19-8FF8-5D852A5F9F0F@gmail.com> References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-12-riel@surriel.com> <40C8627F-0B0B-4F19-8FF8-5D852A5F9F0F@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Mon, 2024-12-30 at 20:25 +0200, Nadav Amit wrote: >=20 > > On 30 Dec 2024, at 19:53, Rik van Riel wrote: > >=20 > > --- a/arch/x86/kernel/cpu/amd.c > > +++ b/arch/x86/kernel/cpu/amd.c > > @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct > > cpuinfo_x86 *c) > >=20 > > /* Max number of pages INVLPGB can invalidate in one shot > > */ > > invlpgb_count_max =3D (edx & 0xffff) + 1; > > + > > + /* If supported, enable translation cache extensions (TCE) > > */ > > + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); > > + if (ecx & BIT(17)) { > > + u64 msr =3D native_read_msr(MSR_EFER);; > > + msr |=3D BIT(15); > > + wrmsrl(MSR_EFER, msr); > > + } > > } >=20 > Sorry for the gradual/delayed feedback. >=20 > Is it possible to avoid the BIT(x) and just add the bits to=20 > arch/x86/include/asm/msr-index.h like EFER_FFXSR ? >=20 Of course! I'd be happy to send that either as part of the next version of the patch series, or as a separate cleanup patch later. Whatever is more convenient for the x86 maintainers. --=20 All Rights Reversed.