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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI0MDA0NSBTYWx0ZWRfX80V9AuIfyYr9 BWNyrY/2u7GbgnGR8HrUSt7S7bI6hnkN4wVlKaW2ikyQ9xTaR4odZiZ2vCY/CdEEn36QJHAPmh8 F/Rzf43d9wNcykHZNuPbNvo3XbSdJdMUeXBLHpXO3qvL9der7bLwSup1K4vxS1arQNSyLWY2wu3 LQDDVporUSfv6VPFdZjBZ9bU/o3V0xI1zAD0TMYSeuLmh4FpPnY0k7h74Rm+fUUEnX1HiZlmC2k 3OHUFJsKTsMHtbLKdrxicBb90Ch7b27O4oQM0UkK3uIdg7mT6UUIM5OrkYvNIAByWN7oPTzyy/C zpJSGEA/m7kDXTcJYVVt5p6LiSgoN6BynbkIqF5mfcdRSAMSTECfKIeIwkPts0BeM8p6R40lzHN Ed0nZrKlEe7H8K5hFIikP1EMtwjdAXioCvdVhxW2TINn3ieqRljD+96wgd2878eYhZJEoWCUolX iFrXOrCDfjTZdXg5JGw== X-Proofpoint-GUID: nTO9g1YWUBUM-inlyHrzbcqUlS9MIo1_ X-Authority-Analysis: v=2.4 cv=Z5Lh3XRA c=1 sm=1 tr=0 ts=699d3848 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Ym3PPFOpFhoklKWBbF8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: nTO9g1YWUBUM-inlyHrzbcqUlS9MIo1_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_06,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602240045 On 2/23/2026 7:27 PM, Shawn Lin wrote: > Hi Krishna, > > 在 2026/02/23 星期一 19:13, Krishna Chaitanya Chundru 写道: >> Some platforms have incorrect T_POWER_ON value programmed in hardware. >> Generally these will be corrected by bootloaders, but not all targets >> support bootloaders to program correct values due to that >> LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which >> can result in improper L1.2 exit behavior and can trigger AER's. >> >> Parse "t-power-on-us" property from each root port node and program them >> as part of host initialization using dw_pcie_program_t_power_on() before >> link training. >> >> This property in added to the dtschema here[1]. >> >> Signed-off-by: Krishna Chaitanya Chundru >> >> Link[1]: >> https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/ >> --- >>   drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++ >>   1 file changed, 15 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >> b/drivers/pci/controller/dwc/pcie-qcom.c >> index >> 67a16af69ddc75fca1b123e70715e692a91a9135..489ed64c1df0fa3ed9f6b0d4c3e0bb65cfc3308e >> 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -269,6 +269,7 @@ struct qcom_pcie_perst { >>   struct qcom_pcie_port { >>       struct list_head list; >>       struct phy *phy; >> +    u32 t_power_on; >>       struct list_head perst; >>   }; >>   @@ -1283,6 +1284,16 @@ static int qcom_pcie_phy_power_on(struct >> qcom_pcie *pcie) >>       return 0; >>   } >>   +static int qcom_pcie_configure_ports(struct qcom_pcie *pcie) >> +{ >> +    struct qcom_pcie_port *port; >> + >> +    list_for_each_entry(port, &pcie->ports, list) >> +        dw_pcie_program_t_power_on(pcie->pci, port->t_power_on); >> + >> +    return 0; >> +} >> + >>   static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >>   { >>       struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> @@ -1317,6 +1328,8 @@ static int qcom_pcie_host_init(struct >> dw_pcie_rp *pp) >>       dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); >>       dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); >>   +    qcom_pcie_configure_ports(pcie); >> + >>       qcom_pcie_perst_deassert(pcie); >>         if (pcie->cfg->ops->config_sid) { >> @@ -1759,6 +1772,8 @@ static int qcom_pcie_parse_port(struct >> qcom_pcie *pcie, struct device_node *node >>       if (ret) >>           return ret; >>   +    of_property_read_u32(node, "t-power-on-us", &port->t_power_on); > > Your patch 2 adds a common helper in pcie-designware, but why not add > this parse as well as what the qcom_pcie_configure_ports() does, into to > the pcie-designware core, etc dw_pcie_host_init()/dw_pcie_ep_init()? > Because I don't see anything qcom specific here. > Currently dwc doesn't support to read multiple root ports, but these properties needs to be read from root ports. For that reason I kept it in qcom driver until dwc supports multi root ports parsing which is currently in process. - Krishna Chaitanya. > >> + >>       port->phy = phy; >>       INIT_LIST_HEAD(&port->list); >>       list_add_tail(&port->list, &pcie->ports); >>