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Fri, 16 Oct 2026 03:46:40 -0700 (PDT) Message-ID: Date: Fri, 16 Oct 2026 11:46:39 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/8] phy: rockchip-samsung-dcphy: Move block-level setup to runtime resume To: Jason Yang , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: Michael Riesch , Sebastian Reichel , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20261016-dcphy-rx-v1-v5-0-e63b49eabe2d@gmail.com> <20261016-dcphy-rx-v1-v5-3-e63b49eabe2d@gmail.com> From: Bryan O'Donoghue Content-Language: en-GB In-Reply-To: <20261016-dcphy-rx-v1-v5-3-e63b49eabe2d@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 16/10/2026 09:56, Jason Yang wrote: > Program them from runtime resume instead, where whichever of the two > comes up first brings the block up and a second one no longer resets it. > This puts the BIAS writes ahead of the per-PHY reset assert, where the > TRM's worked example has them after [1]. That is safe: neither M_RESETN > nor S_RESETN covers the BIAS registers, and the values written are those > registers' reset defaults. Would you not be better off scheduling a work job when you know both blocks are out of suspend ? That way you always have a known sequence out of reset ? --- bod