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Wed, 28 Jan 2026 21:29:42 -0800 (PST) X-Received: by 2002:a17:903:22d2:b0:2a7:5751:5b27 with SMTP id d9443c01a7336-2a870e192ecmr74202455ad.39.1769664582284; Wed, 28 Jan 2026 21:29:42 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b3faff5sm37408765ad.4.2026.01.28.21.29.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jan 2026 21:29:41 -0800 (PST) Message-ID: Date: Thu, 29 Jan 2026 10:59:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] PCI: qcom: Add D3cold support To: Bjorn Andersson Cc: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com References: <20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com> <20260128-d3cold-v1-3-dd8f3f0ce824@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 1gsmj36D2iWx5PAH0eA8lCTsK_YbpR6e X-Proofpoint-GUID: 1gsmj36D2iWx5PAH0eA8lCTsK_YbpR6e X-Authority-Analysis: v=2.4 cv=J/inLQnS c=1 sm=1 tr=0 ts=697af047 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=24nHYv6InDTK1t9ftLgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDAzMyBTYWx0ZWRfX+pUi+qYn8rKd LEJdhYVg9tlrSh9UVGMYy303UVxkVYIq8USPKZ7WjFo9GuTsO3yfpKEYYa/1iSnxoviqoTSj5wN Za7+oZpTDj5lNoDL9ccF8eBNd/+h4p2Cu0sCaj6k7ZP8Lc9YCvepF7PKEhrkzKDm6Hk4GsAbeGG m47WFZKH43BFiptPb6k/yd0t9LAVmwoIg6X8X7gxoVdSL5FlX+RoIlbnW+YfFA1WlT6rIqiTAr2 U9n8Eh6/+rRwTFDutQngkMdeQsKBFPDyKzgq72HwH3ACCUu+BUUbk2dXiIR3pGBh8VjHLMHWdbT 2+W6rZXdf0GjKDy5w+qYlf85I7G0HKpNQdWf7HjtaloQ8Zpa2LzfmAlu/Jt0ZAbAO+pCrrmBKzY t966oYUw/upcJsqQwicxha7h40ZmjY+iw8Bgj/GTIT7DPphE5IZ6YVgcJW125v/M31YKS/avV/Y Dbtnu39OxKDRv8oJGSw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_06,2026-01-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601290033 On 1/28/2026 8:17 PM, Bjorn Andersson wrote: > On Wed, Jan 28, 2026 at 05:10:43PM +0530, Krishna Chaitanya Chundru wrote: >> Add pme_turn_off() support and use DWC common suspend resume methods >> for device D3cold entry & exit. If the device is not kept in D3cold >> use existing methods like keeping icc votes, opp votes etc.. intact. >> >> In qcom_pcie_deinit_2_7_0(), explicitly disable PCIe clocks and resets >> in the controller. >> >> Remove suspended flag from qcom_pcie structure as it is no longer needed. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++++++------------- >> 1 file changed, 68 insertions(+), 46 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > [..] >> @@ -2016,53 +2030,51 @@ static int qcom_pcie_suspend_noirq(struct device *dev) >> if (!pcie) >> return 0; >> >> - /* >> - * Set minimum bandwidth required to keep data path functional during >> - * suspend. >> - */ >> - if (pcie->icc_mem) { >> - ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); >> - if (ret) { >> - dev_err(dev, >> - "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", >> - ret); >> - return ret; >> - } >> - } >> + ret = dw_pcie_suspend_noirq(pcie->pci); >> + if (ret) >> + return ret; >> >> - /* >> - * Turn OFF the resources only for controllers without active PCIe >> - * devices. For controllers with active devices, the resources are kept >> - * ON and the link is expected to be in L0/L1 (sub)states. >> - * >> - * Turning OFF the resources for controllers with active PCIe devices >> - * will trigger access violation during the end of the suspend cycle, >> - * as kernel tries to access the PCIe devices config space for masking >> - * MSIs. >> - * >> - * Also, it is not desirable to put the link into L2/L3 state as that >> - * implies VDD supply will be removed and the devices may go into >> - * powerdown state. This will affect the lifetime of the storage devices >> - * like NVMe. >> - */ >> - if (!dw_pcie_link_up(pcie->pci)) { >> - qcom_pcie_host_deinit(&pcie->pci->pp); >> - pcie->suspended = true; >> - } >> + if (pcie->pci->suspended) { > I think this is okay for now, but I'd prefer changing the return value > of dw_pcie_suspend_noirq() to indicate if it did stop the link or not > (two different success values) - rather than deriving that information > by peeking into the dw_pcie struct and conclude that > dw_pcie_suspend_noirq() did reach the end. > >> + ret = icc_disable(pcie->icc_mem); >> + if (ret) >> + dev_err(dev, "Failed to disable PCIe-MEM interconnect path: %d\n", ret); >> >> - /* >> - * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. >> - * Because on some platforms, DBI access can happen very late during the >> - * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC >> - * error. >> - */ >> - if (pm_suspend_target_state != PM_SUSPEND_MEM) { >> ret = icc_disable(pcie->icc_cpu); >> if (ret) >> dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); >> >> if (pcie->use_pm_opp) >> dev_pm_opp_set_opp(pcie->pci->dev, NULL); >> + } else { >> + /* >> + * Set minimum bandwidth required to keep data path functional during >> + * suspend. >> + */ >> + if (pcie->icc_mem) { >> + ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); >> + if (ret) { >> + dev_err(dev, >> + "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", >> + ret); >> + return ret; >> + } >> + } >> + >> + /* >> + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. >> + * Because on some platforms, DBI access can happen very late during the >> + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC >> + * error. >> + */ >> + if (pm_suspend_target_state != PM_SUSPEND_MEM) { >> + ret = icc_disable(pcie->icc_cpu); >> + if (ret) >> + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", >> + ret); >> + >> + if (pcie->use_pm_opp) >> + dev_pm_opp_set_opp(pcie->pci->dev, NULL); >> + } >> } >> return ret; >> } >> @@ -2076,20 +2088,30 @@ static int qcom_pcie_resume_noirq(struct device *dev) >> if (!pcie) >> return 0; >> >> - if (pm_suspend_target_state != PM_SUSPEND_MEM) { >> + if (pcie->pci->suspended) { >> ret = icc_enable(pcie->icc_cpu); >> if (ret) { >> dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); >> return ret; >> } >> - } >> >> - if (pcie->suspended) { >> - ret = qcom_pcie_host_init(&pcie->pci->pp); >> + ret = icc_enable(pcie->icc_mem); >> + if (ret) { >> + dev_err(dev, "Failed to enable PCIe-MEM interconnect path: %d\n", ret); > I think you should revert icc_enable(pcie->icc_cpu) here, to avoid > leaving the bus voted for with the PCIe controller resume aborted. > >> + return ret; >> + } >> + ret = dw_pcie_resume_noirq(pcie->pci); >> if (ret) > And Both icc_cpu and icc_mem here. Ack, I will do this in V2. - Krishna Chaitanya. > Regards, > Bjorn > >> return ret; >> - >> - pcie->suspended = false; >> + } else { >> + if (pm_suspend_target_state != PM_SUSPEND_MEM) { >> + ret = icc_enable(pcie->icc_cpu); >> + if (ret) { >> + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", >> + ret); >> + return ret; >> + } >> + } >> } >> >> qcom_pcie_icc_opp_update(pcie); >> >> -- >> 2.34.1 >> >>