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Thu, 17 Oct 2024 14:11:40 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94E4F2004B; Thu, 17 Oct 2024 14:11:40 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2ED5520043; Thu, 17 Oct 2024 14:11:35 +0000 (GMT) Received: from [9.61.240.109] (unknown [9.61.240.109]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 17 Oct 2024 14:11:34 +0000 (GMT) Message-ID: Date: Thu, 17 Oct 2024 19:41:33 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 1/2] tools/perf/pmu-events/powerpc: Add support for compat events in json To: Athira Rajeev , acme@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, irogers@google.com, namhyung@kernel.org, hbathini@linux.ibm.com Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, akanksha@linux.ibm.com, maddy@linux.ibm.com, kjain@linux.ibm.com References: <20241010145107.51211-1-atrajeev@linux.vnet.ibm.com> Content-Language: en-GB From: Disha Goel In-Reply-To: <20241010145107.51211-1-atrajeev@linux.vnet.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: BtHeLm8IZStEeRWZEcfiThbb-aaO-liC X-Proofpoint-ORIG-GUID: Q5jCgTE8keNmh0JEKGZWAZNTElHQWOGu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 spamscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170096 On 10/10/24 8:21 pm, Athira Rajeev wrote: > perf list picks the events supported for specific platform > from pmu-events/arch/powerpc/. Example power10 events > are in pmu-events/arch/powerpc/power10, power9 events are part > of pmu-events/arch/powerpc/power9. The decision of which > platform to pick is determined based on PVR value in powerpc. > The PVR value is matched from pmu-events/arch/powerpc/mapfile.csv > > Example: > > Format: > PVR,Version,JSON/file/pathname,Type > > 0x004[bcd][[:xdigit:]]{4},1,power8,core > 0x0066[[:xdigit:]]{4},1,power8,core > 0x004e[[:xdigit:]]{4},1,power9,core > 0x0080[[:xdigit:]]{4},1,power10,core > 0x0082[[:xdigit:]]{4},1,power10,core > > The code gets the PVR from system using get_cpuid_str function > in arch/powerpc/util/headers.c ( from SPRN_PVR ) and compares > with value from mapfile.csv > > In case of compat mode, say when partition is booted in a power9 > mode when the system is a power10, add an entry to pick the > ISA architected events from "pmu-events/arch/powerpc/compat". > Add json file generic-events.json which will contain these > events which is supported in compat mode. > > Suggested-by: Madhavan Srinivasan > Signed-off-by: Athira Rajeev I have tested the patch on PowerPC by booting in different compat modes and at base also, and it's working as expected. For the series: Tested-by: Disha Goel > --- > > .../arch/powerpc/compat/generic-events.json | 117 ++++++++++++++++++ > .../perf/pmu-events/arch/powerpc/mapfile.csv | 1 + > 2 files changed, 118 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/powerpc/compat/generic-events.json > > diff --git a/tools/perf/pmu-events/arch/powerpc/compat/generic-events.json b/tools/perf/pmu-events/arch/powerpc/compat/generic-events.json > new file mode 100644 > index 000000000000..6f5e8efcb098 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/powerpc/compat/generic-events.json > @@ -0,0 +1,117 @@ > +[ > + { > + "EventCode": "0x600F4", > + "EventName": "PM_CYC", > + "BriefDescription": "Processor cycles." > + }, > + { > + "EventCode": "0x100F2", > + "EventName": "PM_CYC_INST_CMPL", > + "BriefDescription": "1 or more ppc insts finished" > + }, > + { > + "EventCode": "0x100f4", > + "EventName": "PM_FLOP_CMPL", > + "BriefDescription": "Floating Point Operations Finished." > + }, > + { > + "EventCode": "0x100F6", > + "EventName": "PM_L1_ITLB_MISS", > + "BriefDescription": "Number of I-ERAT reloads." > + }, > + { > + "EventCode": "0x100F8", > + "EventName": "PM_NO_INST_AVAIL", > + "BriefDescription": "Number of cycles the ICT has no itags assigned to this thread." > + }, > + { > + "EventCode": "0x100fc", > + "EventName": "PM_LD_CMPL", > + "BriefDescription": "Load instruction completed." > + }, > + { > + "EventCode": "0x200F0", > + "EventName": "PM_ST_CMPL", > + "BriefDescription": "Stores completed from S2Q (2nd-level store queue)." > + }, > + { > + "EventCode": "0x200F2", > + "EventName": "PM_INST_DISP", > + "BriefDescription": "PowerPC instruction dispatched." > + }, > + { > + "EventCode": "0x200F4", > + "EventName": "PM_RUN_CYC", > + "BriefDescription": "Processor cycles gated by the run latch." > + }, > + { > + "EventCode": "0x200F6", > + "EventName": "PM_L1_DTLB_RELOAD", > + "BriefDescription": "DERAT Reloaded due to a DERAT miss." > + }, > + { > + "EventCode": "0x200FA", > + "EventName": "PM_BR_TAKEN_CMPL", > + "BriefDescription": "Branch Taken instruction completed." > + }, > + { > + "EventCode": "0x200FC", > + "EventName": "PM_L1_ICACHE_MISS", > + "BriefDescription": "Demand instruction cache miss." > + }, > + { > + "EventCode": "0x200FE", > + "EventName": "PM_L1_RELOAD_FROM_MEM", > + "BriefDescription": "L1 Dcache reload from memory" > + }, > + { > + "EventCode": "0x300F0", > + "EventName": "PM_ST_MISS_L1", > + "BriefDescription": "Store Missed L1" > + }, > + { > + "EventCode": "0x300FC", > + "EventName": "PM_DTLB_MISS", > + "BriefDescription": "Data PTEG reload" > + }, > + { > + "EventCode": "0x300FE", > + "EventName": "PM_DATA_FROM_L3MISS", > + "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)" > + }, > + { > + "EventCode": "0x400F0", > + "EventName": "PM_LD_MISS_L1", > + "BriefDescription": "L1 Dcache load miss" > + }, > + { > + "EventCode": "0x400F2", > + "EventName": "PM_CYC_INST_DISP", > + "BriefDescription": "Cycle when instruction(s) dispatched." > + }, > + { > + "EventCode": "0x400F6", > + "EventName": "PM_BR_MPRED_CMPL", > + "BriefDescription": "A mispredicted branch completed. Includes direction and target." > + }, > + { > + "EventCode": "0x400FA", > + "EventName": "PM_RUN_INST_CMPL", > + "BriefDescription": "PowerPC instruction completed while the run latch is set." > + }, > + { > + "EventCode": "0x400FC", > + "EventName": "PM_ITLB_MISS", > + "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses." > + }, > + { > + "EventCode": "0x400fe", > + "EventName": "PM_LD_NOT_CACHED", > + "BriefDescription": "Load data not cached." > + }, > + { > + "EventCode": "0x500fa", > + "EventName": "PM_INST_CMPL", > + "BriefDescription": "Instructions." > + } > +] > diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv > index 4d5e9138d4cc..cbd3cb443784 100644 > --- a/tools/perf/pmu-events/arch/powerpc/mapfile.csv > +++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv > @@ -16,3 +16,4 @@ > 0x004e[[:xdigit:]]{4},1,power9,core > 0x0080[[:xdigit:]]{4},1,power10,core > 0x0082[[:xdigit:]]{4},1,power10,core > +0x00ffffff,1,compat,core