From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756279AbeDZNfu (ORCPT ); Thu, 26 Apr 2018 09:35:50 -0400 Received: from mail-sn1nam02on0081.outbound.protection.outlook.com ([104.47.36.81]:4736 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754847AbeDZNfp (ORCPT ); Thu, 26 Apr 2018 09:35:45 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Subject: Re: [PATCH] gpio: zynq: Setup chip->base based on alias ID To: Linus Walleij , Michal Simek CC: "linux-kernel@vger.kernel.org" , Michal Simek , Steffen Trumtrar , Peter Crosthwaite , "open list:GPIO SUBSYSTEM" , Rob Herring , Linux ARM References: <6ee982f8eb6e07f9ecbb0cc5093152f4a16b9c31.1523454899.git.michal.simek@xilinx.com> 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1;CY1PR02MB1676;7:UjjuGggr7fE+MM2hA98PjGRhzx/TyWfoSzPzohvwIZkhzOYuuggH9EWFpoyvoKczs7JMHO/6ubhieoFt00ofbNoshTfhhgx2utMQywBcNPi67t4YVD3gOVft7F4pupfpOlqGfQLAQbUeUfkIEk0c4xAZ+UeejKDzyyYaQC4ltKwlvuJU8sJkIw3HjCXRvyWZeAC1yCzU/9RbtgIPo78n8QMwcx04/B3azhrQqqnJJQ3/3zoX+KDo40M8SQCWj+Hj X-MS-Office365-Filtering-Correlation-Id: 06456895-fda5-4592-9849-08d5ab7a9be7 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2018 13:35:42.9518 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06456895-fda5-4592-9849-08d5ab7a9be7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1676 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, On 26.4.2018 15:08, Linus Walleij wrote: > On Wed, Apr 11, 2018 at 3:55 PM, Michal Simek wrote: > > Thanks for your patch! > >> In past Xilinx gpio-zynq driver was setting up gpio chip->base as 0 >> which was chagned to autodetection when driver was upstreamed. Older >> systems, which were using this old version, setup SW stack which expects >> zynq gpio base as 0 and right now there is no way how to set this up. >> >> The patch is adding an option to setup chip->base based on aliases which >> is something what some other drivers are doing too. >> It means when gpio0 alias is setup then chip->base is 0. When gpio alias >> is not setup gpiochip_find_base() set it up properly which is current >> behavior. >> >> Signed-off-by: Michal Simek > > In general, we stopped any controlling of the GPIO base. I know. > > Also this use would have to be OK with the DT maintainers > as I never saw this use of alias before. If you grep gpio drivers you will see that these gpio-zx, gpio-mvebu, gpio-mxc, gpio-mxs, gpio-vf610 are using that. > > Please describe the use case for this. > > The only use case which I can think about is userspace sysfs > and then I would really like to know why these userspace > users cannot use the character device that is nowadays > supported by libgpiod and there is even patches for some > IoT libraries to use it. The character device makes the > GPIO Linux "base" irrelevant for userspace. > > GPIO sysfs is deprecated and moved to the obsolete ABI. > > If there are legacy applications that use this I would have > to consider it, but since this has been -1 since the driver > was merged I find that unlikely. Yes, it is about legacy application which I have seen recently and there is no source code for application calls it because board vendor doesn't provide it. You are right that -1 was used from the beginning in mainline but unfortunately this driver was in vendor tree for a while and it uses 0 there. In upstreaming this was changed to -1 but customers have a lot of code which developed against vendor tree and they want to use latest&greatest. And without this they are not able to run that applications. I found that this logic is already in 5 drivers in mainline that's why I send this patch to be +1. Thanks, Michal