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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from CY5PR12MB6252.namprd12.prod.outlook.com (2603:10b6:930:20::17) by CH8PR12MB9744.namprd12.prod.outlook.com (2603:10b6:610:27a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.9; Fri, 30 Oct 2026 12:56:13 +0000 Received: from CY5PR12MB6252.namprd12.prod.outlook.com ([fe80::ab00:d77:6014:64a2]) by CY5PR12MB6252.namprd12.prod.outlook.com ([fe80::ab00:d77:6014:64a2%4]) with mapi id 15.21.0569.009; Fri, 30 Oct 2026 12:56:13 +0000 Message-ID: Date: Fri, 30 Oct 2026 18:25:07 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 20/21] soundwire: amd: Check clock resume timeout in amd_resume_runtime() From: "Mukunda,Vijendar" To: Lee Jones , Vinod Koul , Bard Liao , Pierre-Louis Bossart , Mastan Katragadda , linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org, Mario Limonciello , Syed Saba Kareem , "Dommati, Sunil-kumar" , "Prasad, Prasad" , "N, Poojitha" Cc: stable@vger.kernel.org References: <20261030104840.3361217-1-lee@kernel.org> <20261030104840.3361217-21-lee@kernel.org> <55ccb8c9-9d11-4c22-b17d-a31746ea4031@amd.com> Content-Language: en-US In-Reply-To: <55ccb8c9-9d11-4c22-b17d-a31746ea4031@amd.com> Content-Type: text/plain; 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>> -            if (val & AMD_SDW_CLK_RESUME_DONE) { >> -                writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); >> -                amd_manager->clk_stopped = false; >> -            } >> +            if (ret) >> +                return ret; >> +            writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); >> +            amd_manager->clk_stopped = false; > ++ > > The bug is valid. On clock resume timeout the code falls through to > sdw_clear_slave_status() and full bus re-init without the clock > being active, which is incorrect. > > However, we have identified additional issues in this code path that > need to be addressed together: > > 1. writel(0, ACP_SW_CLK_RESUME_CTRL) is incorrect — this register >    is not a plain zero-clear register. Only the Clk_Resume_Req bit >    should be cleared using a read-modify-write on the success path. Slight correction.  Ignore comment 1. > > 2. The same unchecked ret pattern exists in >    amd_acp63_sdw_clock_stop_exit() and needs to be fixed together. > > We are planning to address all of these as part of our upcoming v4 > patch series which will be posted shortly. Could you please hold > this patch until v4 is on-list to avoid conflicts? >>           } >>           sdw_clear_slave_status(bus, >> SDW_UNATTACH_REQUEST_MASTER_RESET); >>           ret = amd_sdw_clk_init_ctrl(amd_manager); >