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Sun, 06 Sep 2026 22:14:32 -0700 (PDT) X-Received: by 2002:a05:6a21:114c:b0:3d1:e510:9052 with SMTP id adf61e73a8af0-3da39ee2689mr32370785637.7.1788758071745; Sun, 06 Sep 2026 22:14:31 -0700 (PDT) Received: from [10.217.219.15] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339885ca07sm27645812eec.1.2026.09.06.22.14.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Sep 2026 22:14:31 -0700 (PDT) Message-ID: Date: Mon, 7 Sep 2026 10:44:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/3] dmaengine: qcom: gpi: Add I2C bus recovery opcode support To: Aniket Randive , Vinod Koul , Frank Li , Viken Dadhaniya , Andi Shyti Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260826-i2c_bus_recovery-v1-0-203f0ec76f84@oss.qualcomm.com> <20260826-i2c_bus_recovery-v1-1-203f0ec76f84@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20260826-i2c_bus_recovery-v1-1-203f0ec76f84@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: AAaNJG3LfeG8lwaOhZXXYa1BNWFlLXDq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDA1MyBTYWx0ZWRfX5mm7X6AgWnVo G+mETB5erSwmXAUdZ/OgYtraS2GSnEXkb9DWXuJTa9muuQxowH3mLSDnnoCRIJtnlOmRW0GPgHY cV34xd+Xsf+IgoR+/XQ3V5MXwY9X98OykBIbhRSXJ7SlrqsyY8PDpRW4nHvchmRyjPaqHYrTebp TRjJAk+ZZB8Q/iYaywrNMoftH6aWGLAdUC6qQ/aBi8iDdRV1hjsTWDCpdB9ypjfreDbibHLVlb/ F4pmv1Au3gENAS61uZ8wBD22Hc0blKVHAYIfDwrt+qgEQk0pFe50qu8Z0w8nTFagUGBmQLgU77B VCgcRgiVEsWTpSw5GArBTpztfNv4Y97efvlxLLf/T0NnGhmG5faxiYQBZFIH3vdYU+V2cFFeUvR PSXAecTWZqcLGH55KgPFRo8KKWHVFWwggo4clJvm+Rqsaue0wuasLVBd5oqyWlPhJ0G9D/Hoidn L5+JeUvkyLWXm3eiLMw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDA1MyBTYWx0ZWRfXxySCgiPzhC96 FeLcpF8lbNJ5OpbRtd6iKG1yFWtM0Qd0DhBSs1FniWHM2fGtPu8S0N8Quxl6e3tkGsKdyCy9VJO aldcybIPYGosVzlJ1ShDIVYZZxw9DHk= X-Authority-Analysis: v=2.4 cv=OceoyBTY c=1 sm=1 tr=0 ts=6a9e4838 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=fhPPmUa07wtAw6AntU8A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: AAaNJG3LfeG8lwaOhZXXYa1BNWFlLXDq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_01,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070053 On 8/26/2026 3:21 PM, Aniket Randive wrote: > The I2C_BUS_CLEAR and I2C_STOP_ON_BUS GENI sequencer opcodes release a > stuck I2C bus, but the GPI DMA driver has no way to emit these > zero-payload control commands, so an I2C controller using GPI DMA > cannot recover the bus. > > Add I2C_BUS_CLEAR and I2C_STOP_ON_BUS to enum i2c_op so I2C drivers can > request them through gpi_i2c_config.op. Handle them in > gpi_create_i2c_tre() by emitting a CONFIG TRE (when set_config is set) > followed by a GO TRE with IEOT set and no DMA TRE, and reserve the > matching number of ring entries in gpi_prep_slave_sg(). > start with problem statement which is being fixed by the respective patch. Rest of the message can be simplified as below - more you can add. Allow GPI DMA clients to issue the GENI I2C_BUS_CLEAR and I2C_STOP_ON_BUS commands used for I2C bus recovery. Add the new opcodes to the GPI I2C interface and generate the corresponding CONFIG/GO TRE sequence without data DMA transfers. Adjust TRE reservation logic to account for these commands. > Signed-off-by: Aniket Randive > --- > drivers/dma/qcom/gpi.c | 30 ++++++++++++++++++++++++++++++ > include/linux/dma/qcom-gpi-dma.h | 2 ++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c [...] > @@ -1825,6 +1843,18 @@ gpi_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, > nr_tre = 2; > if (direction == DMA_DEV_TO_MEM) /* rx */ > nr_tre = 1; > + /* > + * Recovery opcodes do not require DMA data TREs, only CONFIG > + * (for set_config) and GO TREs. Since gpi_prep_slave_sg() is > + * shared with SPI, verify the channel is I2C before accessing Not only SPI, its for all GENI protocols. Can say common function for all protocols. May be once such conditions are rising, we need to think of better way in design to handle such cases. > + * the configuration data. > + */ > + if (gchan->protocol == QCOM_GPI_I2C) { > + struct gpi_i2c_config *i2c = gchan->config; > + > + if (i2c->op == I2C_BUS_CLEAR || i2c->op == I2C_STOP_ON_BUS) > + nr_tre = set_config ? 2 : 1; > + } > [...]