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> int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, > cpumask_t *affinity); > > +/* > + * MPAM MSCs have the following register layout. See: > + * Arm Memory System Resource Partitioning and Monitoring (MPAM) System > + * Component Specification. > + * https://developer.arm.com/documentation/ihi0099/latest/ > + */ > +#define MPAM_ARCHITECTURE_V1 0x10 > + > +/* Memory mapped control pages */ > +/* ID Register offsets in the memory mapped page */ > +#define MPAMF_IDR 0x0000 /* features id register */ > +#define MPAMF_IIDR 0x0018 /* implementer id register */ > +#define MPAMF_AIDR 0x0020 /* architectural id register */ > +#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ > +#define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ > +#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ > +#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ > +#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ > +#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ > +#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ > +#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ > +#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ > + > +/* Configuration and Status Register offsets in the memory mapped page */ > +#define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ > +#define MPAMCFG_CPBM 0x1000 /* cache-portion config */ > +#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ > +#define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ > +#define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ > +#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ > +#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ > +#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ > +#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ > +#define MPAMCFG_PRI 0x0400 /* priority partitioning config */ > +#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ > +#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ > + > +#define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ > +#define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ > +#define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ > +#define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ > +#define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ > +#define MSMON_CSU 0x0840 /* current cache-usage */ > +#define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ > +#define MSMON_MBWU 0x0860 /* current mem-bw usage value */ > +#define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ > +#define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ > +#define MSMON_MBWU_CAPTURE_L 0x0890 /* last long mem-bw value captured */ > +#define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ > +#define MPAMF_ESR 0x00F8 /* error status register */ > +#define MPAMF_ECR 0x00F0 /* error control register */ > + > +/* MPAMF_IDR - MPAM features ID register */ > +#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) > +#define MPAMF_IDR_PMG_MAX GENMASK(23, 16) > +#define MPAMF_IDR_HAS_CCAP_PART BIT(24) > +#define MPAMF_IDR_HAS_CPOR_PART BIT(25) > +#define MPAMF_IDR_HAS_MBW_PART BIT(26) > +#define MPAMF_IDR_HAS_PRI_PART BIT(27) > +#define MPAMF_IDR_EXT BIT(28) > +#define MPAMF_IDR_HAS_IMPL_IDR BIT(29) > +#define MPAMF_IDR_HAS_MSMON BIT(30) > +#define MPAMF_IDR_HAS_PARTID_NRW BIT(31) > +#define MPAMF_IDR_HAS_RIS BIT(32) > +#define MPAMF_IDR_HAS_EXTD_ESR BIT(38) > +#define MPAMF_IDR_HAS_ESR BIT(39) > +#define MPAMF_IDR_RIS_MAX GENMASK(59, 56) > + > +/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ > +#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) > +#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) > +#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) > + > +/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ > +#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) > + > +/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ > +#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) > +#define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) > +#define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) > +#define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) > +#define MPAMF_CCAP_IDR_NO_CMAX BIT(30) > +#define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) > + > +/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ > +#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) > +#define MPAMF_MBW_IDR_HAS_MIN BIT(10) > +#define MPAMF_MBW_IDR_HAS_MAX BIT(11) > +#define MPAMF_MBW_IDR_HAS_PBM BIT(12) > +#define MPAMF_MBW_IDR_HAS_PROP BIT(13) > +#define MPAMF_MBW_IDR_WINDWR BIT(14) > +#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) > + > +/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ > +#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) > +#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) > +#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) > +#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) > +#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) > +#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) > + > +/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ > +#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) > +#define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) > +#define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) > +#define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) > +#define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) > +#define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) > +#define MPAMF_CSUMON_IDR_CSU_RO BIT(30) > +#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) > + > +/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ > +#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) > +#define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) > +#define MPAMF_MBWUMON_IDR_LWD BIT(29) > +#define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) > +#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) > + > +/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ > +#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) > + > +/* MPAMF_IIDR - MPAM implementation ID register */ > +#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) > +#define MPAMF_IIDR_REVISION GENMASK(15, 12) > +#define MPAMF_IIDR_VARIANT GENMASK(19, 16) > +#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) Just a friendly reminder: v2 defines _SHIFTs for each field in MPAMF_IIDR. They are removed here but will be used in the 2nd series. It's not an issue for this series but just a friendly reminder to add them back in the 2nd series or the mpam/snapshot/6.18-rc1 cannot be built. [SNIP] Thanks. -Fenghua