From: Michael Walle <michael@walle.cc>
To: Richard Cochran <richardcochran@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
"David S . Miller" <davem@davemloft.net>
Subject: Re: [RFC PATCH 0/2] AT8031 PHY timestamping support
Date: Wed, 26 Feb 2020 12:30:48 +0100 [thread overview]
Message-ID: <fa823a08fa6d50c57ca03bdc58bf4921@walle.cc> (raw)
In-Reply-To: <20200226025441.GB10271@localhost>
Am 2020-02-26 03:54, schrieb Richard Cochran:
> On Wed, Feb 26, 2020 at 01:07:26AM +0100, Michael Walle wrote:
>> Am 26. Februar 2020 00:50:40 MEZ schrieb Andrew Lunn <andrew@lunn.ch>:
>> >That sounds fundamentally broken.
>
> Right. It can't work unless the PHY latches the time stamp.
To make things worse, it only has one slot for RX and one slot for TX
timestamps.
>> This might be the case, but the datasheet (some older revision can
>> be found on the internet, maybe you find something) doesn't mention
>> it. Nor does the PTP "guide" (I don't know the exact name, I'd have
>> to check at work) of this PHY. Besides the timestamp there's also
>> the sequence number and the source port id which would need to be
>> read atomically together with the timestamp.
>
> Maybe the part is not intended to be used at all in this way?
>
> AFAICT, PHYs like this are meant to feed a "PTP frame detected" pulse
> into the time stamping unit on the attached MAC. The interrupt serves
> to allow the SW to gather the matching fields from the frame.
But then there would need to be such a hardware pin, correct? Unless
you'd misuse the INT# for it. Also, why should the PHY then have a PHC
which can be adjusted.
>> That sounds fundamentally broken. Which would be odd. Sometimes there
>> is a way to take a snapshot of the value. Reading the first word could
>> trigger this snapshot. Or the last word, or some status register. One
>> would hope the datasheet would talk about this.
>
> This might be the case, but the datasheet (some older revision can
> be found on the internet, maybe you find something) doesn't mention
> it. Nor does the PTP "guide" (I don't know the exact name, I'd have
> to check at work).
BTW, the name of the document is "AR8031 1588v2 Precision Time Protocol,
Application Note, 80-Y0618-15 Rev. A", which describes a use case
where the RTC (ie PHC) is in the AR8031. I don't argue that the PHY is
not broken, only that Atheros at least intended to have that use case.
-michael
next prev parent reply other threads:[~2020-02-26 11:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 23:08 Michael Walle
2020-02-25 23:08 ` [RFC PATCH 1/2] net: phy: let the driver register its own IRQ handler Michael Walle
2020-02-26 7:27 ` Heiner Kallweit
2020-02-26 11:12 ` Michael Walle
2020-02-26 21:17 ` Heiner Kallweit
2020-02-26 22:56 ` Michael Walle
2020-02-25 23:08 ` [RFC PATCH 2/2] net: phy: at803x: add PTP support for AR8031 Michael Walle
2020-02-25 23:50 ` [RFC PATCH 0/2] AT8031 PHY timestamping support Andrew Lunn
2020-02-26 0:07 ` Michael Walle
2020-02-26 2:54 ` Richard Cochran
2020-02-26 11:30 ` Michael Walle [this message]
2020-02-26 14:29 ` Richard Cochran
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