From: Alex Elder <elder@linaro.org>
To: Evan Green <evgreen@chromium.org>
Cc: Arnd Bergmann <arnd@arndb.de>, David Miller <davem@davemloft.net>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Ilias Apalodimas <ilias.apalodimas@linaro.org>,
syadagir@codeaurora.org, mjavid@codeaurora.org,
Ben Chan <benchan@google.com>, Eric Caruso <ejcaruso@google.com>,
abhishek.esse@gmail.com,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 09/18] soc: qcom: ipa: GSI transactions
Date: Mon, 20 May 2019 11:50:06 -0500 [thread overview]
Message-ID: <fa83020a-248c-9686-5a90-81923fe843bb@linaro.org> (raw)
In-Reply-To: <CAE=gft4ZkO+cGMNEt05+Xw=pEoR7gzJ4jBRB9wA0gQ7V=Pag6g@mail.gmail.com>
On 5/20/19 11:34 AM, Evan Green wrote:
> On Mon, May 20, 2019 at 7:44 AM Alex Elder <elder@linaro.org> wrote:
>>
>> On 5/20/19 9:43 AM, Arnd Bergmann wrote:
>>> I have no idea how two 8-bit assignments could do that,
>>> it sounds like a serious gcc bug, unless you mean two
>>> 8-byte assignments, which would be within the range
>>> of expected behavior. If it's actually 8-bit stores, please
>>> open a bug against gcc with a minimized test case.
>>
>> Sorry, it's 8 *byte* assignments, not 8 bit. -Alex
>
> Is it important to the hardware that you're writing all 128 bits of
No, it is not important in the ways you are describing.
We're just geeking out over how to get optimal performance.
A single 128-bit write is nicer than two 64-bit writes,
or more smaller writes.
The hardware won't touch the TRE until the doorbell gets
rung telling it that it is permitted to do so. The doorbell
is an I/O write, which implies a memory barrier, so the entire
TRE will be up-to-date in memory regardless of whether we
write it 128 bits or 8 bits at a time.
-Alex
> this in an atomic manner? My understanding is that while you may get
> different behaviors using various combinations of
> volatile/aligned/packed, this is way deep in the compiler's "free to
> do whatever I want" territory. If the hardware's going to misbehave if
> you don't get an atomic 128-bit write, then I don't think this has
> been nailed down enough, since I think Clang or even a different
> version of GCC is within its right to split the writes up differently.
>
> Is filling out the TRE touching memory that the hardware is also
> watching at the same time? Usually when the hardware cares about the
> contents of a struct, there's a particular (smaller) field that can be
> written out atomically. I remember USB having these structs that
> needed to be filled out, but the hardware wouldn't actually slurp them
> up until the smaller "token" part was non-zero. If the hardware is
> scanning this struct, it might be safer to do it in two steps: 1)
> flush out the filled out struct except for the field with the "go" bit
> (which you'd have zeroed), then 2) set the field containing the "go"
> bit.
>
next prev parent reply other threads:[~2019-05-20 16:50 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-12 1:24 [PATCH 00/18] net: introduce Qualcomm IPA driver Alex Elder
2019-05-12 1:24 ` [PATCH 01/18] bitfield.h: add FIELD_MAX() and field_max() Alex Elder
2019-05-12 6:33 ` Kalle Valo
2019-05-12 12:18 ` Alex Elder
2019-05-12 19:30 ` Johannes Berg
2019-05-12 1:24 ` [PATCH 02/18] soc: qcom: create "include/soc/qcom/rmnet.h" Alex Elder
2019-05-12 2:34 ` Joe Perches
2019-05-12 12:15 ` Alex Elder
2019-05-15 6:59 ` Arnd Bergmann
2019-05-15 12:03 ` Alex Elder
2019-05-16 1:09 ` Subash Abhinov Kasiviswanathan
2019-05-17 17:27 ` Alex Elder
2019-05-17 18:08 ` Subash Abhinov Kasiviswanathan
2019-05-19 17:37 ` Alex Elder
2019-05-12 1:24 ` [PATCH 03/18] dt-bindings: soc: qcom: add IPA bindings Alex Elder
2019-05-15 7:03 ` Arnd Bergmann
2019-05-15 12:04 ` Alex Elder
2019-05-15 16:50 ` Rob Herring
2019-05-15 17:05 ` Alex Elder
2019-05-12 1:24 ` [PATCH 04/18] soc: qcom: ipa: main code Alex Elder
2019-05-12 1:24 ` [PATCH 05/18] soc: qcom: ipa: configuration data Alex Elder
2019-05-12 1:24 ` [PATCH 06/18] soc: qcom: ipa: clocking, interrupts, and memory Alex Elder
2019-05-12 1:24 ` [PATCH 07/18] soc: qcom: ipa: GSI headers Alex Elder
2019-05-12 1:24 ` [PATCH 08/18] soc: qcom: ipa: the generic software interface Alex Elder
2019-05-15 7:21 ` Arnd Bergmann
2019-05-15 12:13 ` Alex Elder
2019-05-15 12:40 ` Arnd Bergmann
2019-05-15 10:47 ` Arnd Bergmann
2019-05-15 13:32 ` Alex Elder
2019-05-15 19:37 ` Arnd Bergmann
2019-05-12 1:24 ` [PATCH 09/18] soc: qcom: ipa: GSI transactions Alex Elder
2019-05-15 7:34 ` Arnd Bergmann
2019-05-15 12:25 ` Alex Elder
2019-05-15 20:50 ` Arnd Bergmann
2019-05-17 18:08 ` Alex Elder
2019-05-17 18:33 ` Arnd Bergmann
2019-05-17 18:44 ` Alex Elder
2019-05-19 17:11 ` Alex Elder
2019-05-20 9:25 ` Arnd Bergmann
2019-05-20 12:50 ` Alex Elder
2019-05-20 14:43 ` Arnd Bergmann
2019-05-20 14:44 ` Alex Elder
2019-05-20 16:34 ` Evan Green
2019-05-20 16:50 ` Alex Elder [this message]
2019-05-20 17:36 ` Evan Green
2019-05-12 1:25 ` [PATCH 10/18] soc: qcom: ipa: IPA interface to GSI Alex Elder
2019-05-12 1:25 ` [PATCH 11/18] soc: qcom: ipa: IPA endpoints Alex Elder
2019-05-12 1:25 ` [PATCH 12/18] soc: qcom: ipa: immediate commands Alex Elder
2019-05-15 8:16 ` Arnd Bergmann
2019-05-15 12:35 ` Alex Elder
2019-05-18 0:34 ` Alex Elder
2019-05-20 14:50 ` Arnd Bergmann
2019-05-20 14:55 ` Alex Elder
2019-05-20 17:35 ` Christoph Hellwig
2019-05-12 1:25 ` [PATCH 13/18] soc: qcom: ipa: IPA network device and microcontroller Alex Elder
2019-05-15 8:21 ` Arnd Bergmann
2019-05-15 12:46 ` Alex Elder
2019-05-12 1:25 ` [PATCH 14/18] soc: qcom: ipa: AP/modem communications Alex Elder
2019-05-12 1:25 ` [PATCH 15/18] soc: qcom: ipa: support build of IPA code Alex Elder
2019-05-12 1:25 ` [PATCH 16/18] MAINTAINERS: add entry for the Qualcomm IPA driver Alex Elder
2019-05-12 1:25 ` [PATCH 17/18] arm64: dts: sdm845: add IPA information Alex Elder
2019-05-12 1:25 ` [PATCH 18/18] arm64: defconfig: enable build of IPA code Alex Elder
2019-05-15 8:23 ` Arnd Bergmann
2019-05-15 12:49 ` Alex Elder
2019-05-15 12:37 ` [PATCH 00/18] net: introduce Qualcomm IPA driver Arnd Bergmann
2019-05-15 12:52 ` Alex Elder
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