From: Jon Hunter <jonathanh@nvidia.com>
To: Ketan Patil <ketanp@nvidia.com>,
krzk@kernel.org, thierry.reding@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v6 0/4] memory: tegra: Add MC error logging support for Tegra264 SoC
Date: Mon, 2 Feb 2026 16:25:15 +0000 [thread overview]
Message-ID: <fa87cec4-1aa8-4e9b-9baa-8b543d2b7c6f@nvidia.com> (raw)
In-Reply-To: <20260130173055.151255-1-ketanp@nvidia.com>
On 30/01/2026 17:30, Ketan Patil wrote:
> In Tegra264, different components from memory subsystems like Memory
> Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS)
> and MC Channels have different interrupt lines for receiving memory
> controller error interrupts. This patch set includes changes to add
> support and enable Memory Controller error logging for Tegra264.
>
> Ketan Patil (4):
> memory: tegra: Group error handling related registers
> memory: tegra: Group register and fields
> memory: tegra: Add support for multiple IRQs
> memory: tegra: Add MC error logging support for Tegra264
>
For the series ...
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Thanks
Jon
--
nvpublic
prev parent reply other threads:[~2026-02-02 16:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-30 17:30 Ketan Patil
2026-01-30 17:30 ` [PATCH v6 1/4] memory: tegra: Group error handling related registers Ketan Patil
2026-01-30 17:30 ` [PATCH v6 2/4] memory: tegra: Group register and fields Ketan Patil
2026-01-30 17:30 ` [PATCH v6 3/4] memory: tegra: Add support for multiple IRQs Ketan Patil
2026-01-30 17:30 ` [PATCH v6 4/4] memory: tegra: Add MC error logging support for Tegra264 Ketan Patil
2026-02-17 8:31 ` Krzysztof Kozlowski
2026-02-18 10:30 ` Ketan Patil
2026-02-02 16:25 ` Jon Hunter [this message]
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