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Mon, 02 Nov 2026 04:58:34 -0800 (PST) Received: from [192.168.0.167] ([64.43.42.35]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b4eca0f376sm3476980a12.26.2026.11.02.04.58.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 04:58:33 -0800 (PST) Message-ID: Date: Mon, 2 Nov 2026 12:58:32 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] media: qcom: camss: Add support for Hawi To: Hangxiang Ma , Bryan O'Donoghue , Nihal Kumar Gupta , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: Suresh Vankadara , Vikram Sharma , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org References: <20261030-hawi-maili-camss-v3-0-9742bca8cef2@oss.qualcomm.com> <20261030-hawi-maili-camss-v3-5-9742bca8cef2@oss.qualcomm.com> <5817be6b-7180-407b-acb5-8c5fdef4edfb@kernel.org> <73b1f591-69cf-471b-9763-a0b719c74501@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-GB In-Reply-To: <73b1f591-69cf-471b-9763-a0b719c74501@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 30/10/2026 15:25, Hangxiang Ma wrote: >> On 30/10/2026 12:43, Nihal Kumar Gupta wrote: >>> +static const struct camss_subdev_resources csid_res_hawi[] = { >>> +    /* CSID0 */ >>> +    { >>> +        .clock = { "csid", "csid_csiphy_rx" }, >>> +        .clock_rate = { { 480000000 }, >>> +                { 480000000 } }, >>> +        .reg = { "csid0" }, >>> +        .interrupt = { "csid0" }, >>> +        .csid = { >>> +            .parent_dev_ops = &vfe_parent_dev_ops, >>> +            .hw_ops = &csid_ops_1190, >>> +            .formats = &csid_formats_gen2 >>> +        } >> >> This looks strange, why is there only one clock rate ? >> >> --- >> bod > Hi Bryan, the current CAMSS CSID code always selects the first frequency > listed for each clock in the CAMSS resource table. > > In camss-csid.c: > > [...] > } else if (clock->nfreqs) { >         clk_set_rate(clock->clk, clock->freq[0]); > } > [...] > > For the CSID and CSID_CSIPHY_RX clocks, the hardware supports three > clock rates: 200 MHz, 300 MHz, and 480 MHz. If I remember correctly, > 200MHz and 300 MHz is not sufficient for the sensor's output pixel rate, > so we need to use the highest rate, 480 MHz, to meet the bandwidth > requirement. Thanks a lot. > > --- > Best Regards, > Hangxiang We have a series from Antans to address this though. We should list the clocks the SoC supports not constrain that list for one specific sensor on a test-case. --- bod