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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61cfc5306e6sm12116057a12.47.2025.09.03.08.50.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Sep 2025 08:50:03 -0700 (PDT) Message-ID: Date: Wed, 3 Sep 2025 17:50:00 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/13] arm64: dts: qcom: lemans-evk: Enable PCIe support To: Wasim Nazir , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Richard Cochran Cc: kernel@oss.qualcomm.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, Sushrut Shree Trivedi References: <20250903-lemans-evk-bu-v2-0-bfa381bf8ba2@oss.qualcomm.com> <20250903-lemans-evk-bu-v2-6-bfa381bf8ba2@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250903-lemans-evk-bu-v2-6-bfa381bf8ba2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 50btrtaScAD1_7y4BFnLIBMuMhxUB4b8 X-Authority-Analysis: v=2.4 cv=Jt/xrN4C c=1 sm=1 tr=0 ts=68b863ad cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=g-wiT8vaiPKb6nfFgJ4A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 50btrtaScAD1_7y4BFnLIBMuMhxUB4b8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAwMSBTYWx0ZWRfXxTP+AHy3xq37 dnjPtfzE5Pi1KR0ep0fm0NJ9npaRFVU527unqfhpSByWERUcSjDN09zfr6dFsvJU4Q2S8MaTMcA yTuVCnIvZPkvSbl5k62igC2Xnf3LgVSXfjSRVXm+mN90yj1j+aXlj2j0L7pIBTFWXBJFr6hs+cw dp0yOoV/x+2zNnkvlTaZ9QojzlRSCCWKmkJWcRMf49LhqypiuPUxciY3j7ng8w63e0vOG71Xmss xQgqIs3D26irulP1e6tSy9LI2deysarvxrTNOsel4pXnvqD7qrLmkeOU84iNqnsxhCMtc+ma45C KRj3XebfS1yaLlpUvlaxquKqxkkioHmsocpfgWpa/C4HYtMEUFT8SA9KMeD1kRgD7Ax7v5WKG3G E+6ohvXB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300001 On 9/3/25 1:47 PM, Wasim Nazir wrote: > From: Sushrut Shree Trivedi > > Enable PCIe0 and PCIe1 along with the respective phy-nodes. > > PCIe0 is routed to an m.2 E key connector on the mainboard for wifi > attaches while PCIe1 routes to a standard PCIe x4 expansion slot. > > Signed-off-by: Sushrut Shree Trivedi > Signed-off-by: Wasim Nazir > --- > arch/arm64/boot/dts/qcom/lemans-evk.dts | 82 +++++++++++++++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts > index 196c5ee0dd34..7528fa1c661a 100644 > --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts > +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts > @@ -379,6 +379,40 @@ &mdss0_dp1_phy { > status = "okay"; > }; > > +&pcie0 { > + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie0_default_state>; property-n property-names in this order, please Konrad