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Tue, 29 Oct 2024 06:08:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49T68ttK031166 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Oct 2024 06:08:55 GMT Received: from [10.204.67.70] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 23:08:51 -0700 Message-ID: Date: Tue, 29 Oct 2024 11:38:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port Content-Language: en-US To: Dmitry Baryshkov CC: , , , , , , , , , , References: <20241008112516.17702-1-quic_mukhopad@quicinc.com> <20241008112516.17702-3-quic_mukhopad@quicinc.com> From: Soutrik Mukhopadhyay In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Pex_-xe5lo-J_Il77HN-WSKvTRynJV8x X-Proofpoint-ORIG-GUID: Pex_-xe5lo-J_Il77HN-WSKvTRynJV8x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=704 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410290047 On 10/28/2024 3:15 PM, Dmitry Baryshkov wrote: > On Mon, 28 Oct 2024 at 10:49, Soutrik Mukhopadhyay > wrote: >> >> On 10/8/2024 5:46 PM, Dmitry Baryshkov wrote: >>> On Tue, Oct 08, 2024 at 04:55:16PM GMT, Soutrik Mukhopadhyay wrote: >>>> Enable DPTX0 and DPTX1 along with their corresponding PHYs for >>>> sa8775p-ride platform. >>> What is connected to those DP lanes? If they are routed directly to the >>> DisplayPort connectors, please add corresponding devices (see >>> dp-connector). >> >> We are defining the functionality of gpio101 and gpio102 as "edp0_hot" >> and "edp1_hot" >> >> respectively. This ensures that the hot plug will be directly routed via >> the display interrupt >> >> line "mdss0" to the display port driver and no external dependencies on >> dp-connector is >> >> necessary. > Please describe the hardware, not the driver necessities. > If the board has a DP connector, please add the node. E.g. it allows > one to specify the label and the type used by the connector. > > Also could you please fix your email client so that you don't have > strange/unnecessary line wraps and empty lines? Addition of DP connector node with the hpd-gpio property does not allow hpd to be detected since the gpio 101/102 have the "edp0_hot" as function. If the hpd-gpio property is removed from the DP connector node, the probe of DP connector will fail. >