From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0CE8C4742C for ; Fri, 30 Oct 2020 21:45:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63E5320727 for ; Fri, 30 Oct 2020 21:45:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725803AbgJ3VpR (ORCPT ); Fri, 30 Oct 2020 17:45:17 -0400 Received: from imap2.colo.codethink.co.uk ([78.40.148.184]:40710 "EHLO imap2.colo.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725767AbgJ3VpR (ORCPT ); Fri, 30 Oct 2020 17:45:17 -0400 X-Greylist: delayed 1513 seconds by postgrey-1.27 at vger.kernel.org; Fri, 30 Oct 2020 17:45:16 EDT Received: from cpc98990-stkp12-2-0-cust216.10-2.cable.virginm.net ([86.26.12.217] helo=[192.168.0.10]) by imap2.colo.codethink.co.uk with esmtpsa (Exim 4.92 #3 (Debian)) id 1kYbox-0007vu-Kv; Fri, 30 Oct 2020 21:20:27 +0000 Subject: Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board To: Anup Patel , Atish Patra Cc: devicetree@vger.kernel.org, Albert Ou , Cyril.Jean@microchip.com, Daire McNamara , Anup Patel , "linux-kernel@vger.kernel.org List" , Rob Herring , Alistair Francis , Paul Walmsley , Palmer Dabbelt , linux-riscv , Padmarao Begari References: <20201028232759.1928479-1-atish.patra@wdc.com> <20201028232759.1928479-3-atish.patra@wdc.com> From: Ben Dooks Organization: Codethink Limited. Message-ID: Date: Fri, 30 Oct 2020 21:20:26 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/10/2020 09:05, Anup Patel wrote: > On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: >> >> Add initial DTS for Microchip ICICLE board having only >> essential devcies (clocks, sdhci, ethernet, serial, etc). >> >> Signed-off-by: Atish Patra >> --- >> arch/riscv/boot/dts/Makefile | 1 + >> arch/riscv/boot/dts/microchip/Makefile | 2 + >> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++ > > I suggest we split this DTS into two parts: > 1. SOC (microchip-polarfire.dtsi) > 2. Board (microchip-icicle-kit-a000.dts) I was just going to suggest that. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html