Re: [PATCH v2] ARM: dts: imx6sx-sdb: Fix enet phy regulator

[Leonard Crestez <leonard.crestez@nxp.com>]

On Thu, 2018-10-04 at 15:47 +0000, Leonard Crestez wrote:
> Bindings for "fixed-regulator" only explicitly support "gpio" property,
> not "gpios". Fix by correcting the property name.
> 
> The enet PHYs on imx6sx-sdb needs to be explicitly reset after a power
> cycle, handle this by adding the phy-reset-gpios property.
> 
> Both phys share a single reset, a scenario similar to imx7d-sdb.
> 
> This issue was exposed by commit efdfeb079cc3 ("regulator: fixed:
> Convert to use GPIO descriptor only") which causes the "gpios" property
> to also be parsed. Before that commit the "gpios" property had no
> effect, PHY reset was only handled in the the bootloader.
> 
> This fixes linux-next boot failures previously reported here:
>  https://lore.kernel.org/patchwork/patch/982437/#1177900
>  https://lore.kernel.org/patchwork/patch/994091/#1178304
> 
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Please hold, this patch still doesn't deal correctly with suspend; link
never comes back up.

It might be better to apply a simpler fix which just keeps reg_enet_3v3
always on.

> 
> ---
>  arch/arm/boot/dts/imx6sx-sdb.dtsi | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> Changes since v1:
>  * Use 0x10b0 for phy reset pinctrl value (Fabio)
>  * Link to v1: https://lore.kernel.org/patchwork/patch/994871/
> 
> diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
> index 53b3408b5fab..29196476ce0c 100644
> --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
> +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
> @@ -115,11 +115,11 @@
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_enet_3v3>;
>  		regulator-name = "enet_3v3";
>  		regulator-min-microvolt = <3300000>;
>  		regulator-max-microvolt = <3300000>;
> -		gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
> +		gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
>  	};
>  
>  	reg_pcie_gpio: regulator-pcie-gpio {
>  		compatible = "regulator-fixed";
>  		pinctrl-names = "default";
> @@ -178,10 +178,11 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_enet1>;
>  	phy-supply = <&reg_enet_3v3>;
>  	phy-mode = "rgmii";
>  	phy-handle = <&ethphy1>;
> +	phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  
>  	mdio {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -371,10 +372,12 @@
>  				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
>  				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
>  				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
>  				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
>  				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
> +				/* phy reset */
> +				MX6SX_PAD_ENET2_CRS__GPIO2_IO_7		0x10b0
>  			>;
>  		};
>  
>  		pinctrl_enet_3v3: enet3v3grp {
>  			fsl,pins = <