From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F252571A0; Thu, 2 Jul 2026 21:08:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783026541; cv=none; b=YtKjo2cl3yHVMv+WU9WQTbIX4hb13PC3UrZ6ebEUH857EiJX8Q9fDTYLG1NmHiss0PjRd/90HYMy64+IBAN7R0UVZ+1Qkx+Dwmhegk8DCDbslCr3UgJOAEQmz7w0lutYh1ytEEnik4iwc7vDqc96G9T4iiB7qIDlMxvOI8jApTs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783026541; c=relaxed/simple; bh=4JophHAYan6pShvOawHRd5pLvehfV5UKdWKk7t7kdzo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=BrYciUA5Rv5+EDxRkj857s9yXUsXjU5JEXWLsd8T0c/J5Ethd+XAF6GurSOp21C8YPgguP+Icu3wHALlk8B89UxmuWGjArwFmAeJOBgTuyOKMMjF7NG6lCfM/Wunq+CX9Dy3VWwI71Ze44V33x77yBdCsJ4QXDnvI2QUDt1UDDs= ARC-Authentication-Results:i=1; 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Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wfOeM-00ARGv-DY; Thu, 02 Jul 2026 23:08:46 +0200 Date: Thu, 2 Jul 2026 23:08:46 +0200 From: Andrew Lunn To: Coia Prant Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Dragan Simic , Jonas Karlman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 3/3] arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2 Message-ID: References: <20260702204628.2407308-2-coiaprant@gmail.com> <20260702204628.2407308-5-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260702204628.2407308-5-coiaprant@gmail.com> > +&gmac0 { > + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; > + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; > + assigned-clock-rates = <0>, <125000000>; > + clock_in_out = "output"; > + pinctrl-names = "default"; > + pinctrl-0 = <&gmac0_miim > + &gmac0_tx_bus2 > + &gmac0_rx_bus2 > + &gmac0_rgmii_clk > + &gmac0_rgmii_bus>; > + phy-handle = <&rgmii_phy0>; > + phy-mode = "rgmii-id"; > + status = "okay"; > +}; > + > +&gmac1 { > + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; > + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; > + assigned-clock-rates = <0>, <125000000>; > + clock_in_out = "output"; > + pinctrl-names = "default"; > + pinctrl-0 = <&gmac1m1_miim > + &gmac1m1_tx_bus2 > + &gmac1m1_rx_bus2 > + &gmac1m1_rgmii_clk > + &gmac1m1_rgmii_bus>; > + phy-handle = <&rgmii_phy1>; > + phy-mode = "rgmii-id"; > + status = "okay"; > +}; > +&mdio0 { > + rgmii_phy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + reset-assert-us = <20000>; > + reset-deassert-us = <100000>; > + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; > + > + leds { > + #address-cells = <1>; > + #size-cells = <0>; > + > + led@1 { > + reg = <1>; > + color = ; > + function = LED_FUNCTION_LAN; > + default-state = "keep"; > + }; > + > + led@2 { > + reg = <2>; > + color = ; > + function = LED_FUNCTION_LAN; > + default-state = "keep"; > + }; > + }; > + }; > +}; > + > +&mdio1 { > + rgmii_phy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + reset-assert-us = <20000>; > + reset-deassert-us = <100000>; > + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; > + > + leds { > + #address-cells = <1>; > + #size-cells = <0>; > + > + led@1 { > + reg = <1>; > + color = ; > + function = LED_FUNCTION_LAN; > + default-state = "keep"; > + }; > + > + led@2 { > + reg = <2>; > + color = ; > + function = LED_FUNCTION_LAN; > + default-state = "keep"; > + }; > + }; > + }; > +}; For these nodes only: Reviewed-by: Andrew Lunn Andrew