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Thu, 28 May 2026 01:00:13 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 11/11] iommu/arm-smmu-v3: Enable PRI for PCI device in arm_smmu_probe_device() Date: Thu, 28 May 2026 00:59:39 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|CH3PR12MB8754:EE_ X-MS-Office365-Filtering-Correlation-Id: 940768bf-5790-4213-5384-08debc8f371c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|7416014|82310400026|6133799003|11063799006|5023799004|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: b8mGDgJFbc7pitL43YO5AFEX6LPDhNIr4R9fpzl0kJepFuau94TFpZ0tfdhFS0cDtMO2sUM6L+NpTqsEsjuXn0KB7mucW5rvyccJ7dES15c/jSQ9FNN2ZT121sbAfSkJhd8rCNqAZTXsuSvkzdzRIH8H2a6aoEb4T31V3Oom9pdhTeRAnzJjH6+AIu8/Xdv/S/ZF2P+F5g2zPF5pOSzLwN+FdHJaE2RlH5VUVjfEhlnO3qtF3skeR0q0/lUSK4o06wMCtAKyCKmaNp3bowkxG1ovHt4mZtBgEOVZm4O5z+DoDIBleaFdSknH2mNClAos/9nROVRNDkfI5ogQ+C9Xk8jlh/8nJ7wslBZjownpk7NN7DrrnAZdcLuAt4ll1ZD7+46SmJsSrfJmNjiZ0ncWi3BvB2GtWcDbaS4C7EgvyIXPYmd+czQfxfNJbW6mV8wQTPD+6vND524bACCRGol2L+7M2Ns5MwPx7w60PB5OOgFRWGzcww5fLxBVG/Qsw4C/b7+Nct2+EzwNad3oXfxEluyEj/q8qVnsS+tvUtonOnCZsicVLIPcEOZ1Ql8sLXG/bgV5ng/0tGDXeh+0KV8vUcSrYswCMKtbfLYQloStHfLyMq052i1P1DfAcEsaYzlvtHgj+6dsNlH2pUZcN7rBz8rLqfrU/hbjbRz9u2e2PabQFx1iWNSSBQkuxOPtvlZjXmRzMRyYbPgcurquSuj/E98ggTpOjdxy5lhEwFkqb10= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(7416014)(82310400026)(6133799003)(11063799006)(5023799004)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZdgdARrmWRd8d7wqNk4UQbHts0xD3XLHkqW0BJRxiQMleZVFfVMxHugUjno8aNophk9qoYPARaerUihz2vevFfcNFwK8YjDSp/ear08xk2TjuLfh8hi3W2RjLMU5N2001wvsdhnq2f4h5tZQ0Ygt3LE5iMrq4aX+X9Uy8GI3EkcmJ+4t7G2rbshyhh6OVm8G4D0QFRbYd3nL771fSD3hiEvy4jPmdQMs1waq6zYjU8Tpjbpn+TC+k201vtNGNQ4D8l3AEQFScP0cLKyDjs39wszBFrEplcJK4b0mq1tk9Drm5SqWx1WO0gT2MsFHW/LE33qI0h1EWjeFZ6AToUlPHBE52xKPIz8V6olsvatyX5cNeA/uptvGonOfN9Y9IUV976EloVW4qeJKkqieV93U/tSfozvtKbsklq2OAaqx5FmF8L73trEyV/GYlXfOWyzy X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 08:00:42.3784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 940768bf-5790-4213-5384-08debc8f371c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8754 Now PRI requests can be correctly handled. Enable the PCI cap when probing a PCI device. Also flush the priq in arm_smmu_attach_release(). Set the per-device outstanding request budget to the full priq depth, same as intel-iommu's per-device PRQ_DEPTH choice. A fixed per-device cap won't prevent multiple PRI-capable devices from potentially exceeding the priq's capacity; priq overflow is recoverable per the SMMUv3 spec, and it is rare in practice. select PCI_PRI in Kconfig like other IOMMUs, gated on PCI so the build can stay clean for non-PCI ARM SMMUv3 configurations. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/Kconfig | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 +++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index 5fac08b89deea..855934d08f866 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -79,6 +79,7 @@ config ARM_SMMU_V3 select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select GENERIC_MSI_IRQ + select PCI_PRI if PCI select IOMMUFD_DRIVER if IOMMUFD help Support for implementations of the ARM System MMU architecture diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 87e4880a145f1..648db9a24b582 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3149,7 +3149,7 @@ static int arm_smmu_enable_iopf(struct arm_smmu_master *master, * device-specific fault handlers and don't need IOPF, so this is not a * failure. */ - if (!master->stall_enabled) + if (!master->stall_enabled && !master->pri_enabled) return 0; /* We're not keeping track of SIDs in fault events */ @@ -3352,6 +3352,12 @@ void arm_smmu_attach_release(struct arm_smmu_attach_state *state) if (smmu->evtq.q.irq) synchronize_irq(smmu->evtq.q.irq); } + /* Drain the hardware priq */ + if (master->pri_enabled) { + arm_smmu_drain_queue_for_iopf(smmu, &smmu->priq.q); + if (smmu->priq.q.irq) + synchronize_irq(smmu->priq.q.irq); + } /* Pending events might be in the combined_irq handler */ if (smmu->combined_irq) synchronize_irq(smmu->combined_irq); @@ -4282,8 +4288,17 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) if (dev_is_pci(dev)) { unsigned int stu = __ffs(smmu->pgsize_bitmap); + struct pci_dev *pdev = to_pci_dev(dev); - pci_prepare_ats(to_pci_dev(dev), stu); + if (!pci_prepare_ats(pdev, stu) && pci_pri_supported(pdev) && + (smmu->features & ARM_SMMU_FEAT_PRI) && smmu->evtq.iopf) { + unsigned int reqs = 1 << smmu->priq.q.llq.max_n_shift; + + if (!pci_reset_pri(pdev) && !pci_enable_pri(pdev, reqs)) + master->pri_enabled = true; + else + dev_warn(master->dev, "failed to enable PRI\n"); + } } return &smmu->iommu; @@ -4299,6 +4314,8 @@ static void arm_smmu_release_device(struct device *dev) WARN_ON(master->iopf_refcount); + if (master->pri_enabled) + pci_disable_pri(to_pci_dev(master->dev)); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); if (arm_smmu_cdtab_allocated(&master->cd_table)) -- 2.43.0