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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a0727c40esm15487188b3a.26.2026.03.17.00.35.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Mar 2026 00:35:44 -0700 (PDT) Message-ID: Date: Tue, 17 Mar 2026 15:35:38 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/12] scsi: ufs: core: Add support for TX Equalization From: Can Guo To: =?UTF-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?= , "beanhuo@micron.com" , "mani@kernel.org" , "avri.altman@wdc.com" , "bvanassche@acm.org" , "martin.petersen@oracle.com" Cc: "linux-scsi@vger.kernel.org" , "adrian.hunter@intel.com" , "alim.akhtar@samsung.com" , "James.Bottomley@HansenPartnership.com" , "quic_nguyenb@quicinc.com" , "linux-kernel@vger.kernel.org" References: <20260308151409.3779137-1-can.guo@oss.qualcomm.com> <20260308151409.3779137-5-can.guo@oss.qualcomm.com> <42587e16218f1c51dbcbe6bb1639a843e10bcd80.camel@mediatek.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: oB0NKnggttEU6xDAEk5ryX1HyzQ_ake6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDA2NSBTYWx0ZWRfXznea0ui9Mhb8 nCYQ6P5P4Kkwvi6BKYsvTqd1NJacNCbySvDikdwTjDhlDCAzlp6M8wGib8UrUG1Qt906oy3FG1J lh6p0NWrqKdT8Y5iaRA5ABqXmfoUS2BDed0Ru59/P9aEUDXfhlLLcey2r3myLg2DcZLAjK1bkga uCaZ/YTia2ly9W+VxPZjmx+Kf/SW78Zaw6QdLsxKQ+m6ha2k9VMWYsU9ldHKpW6Ktk8NdjYCczv Re3IoghHS5iQlf5DrP1eIAq8TUoiywimGMQGvOfiLZDJC1tag61S9LSZ+Sp8sSNTT4fC3fcV2I3 6oHJVKwATbRybIiRdKbloyPMKlIMsS39BHQBha9/bZzp+WAAW0Y7vQFbEgZohgUqflSG+8UYwzy SVhx0tNIN0Sr6SeMfdZozQ+euWYNjVKFe2K5IaQ7ZdsllAVcemw62kGlcFdmCvHKpGBnRH5M08B Ump6jvEmBKxpz0eSPlQ== X-Authority-Analysis: v=2.4 cv=fa6gCkQF c=1 sm=1 tr=0 ts=69b90452 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=sVS9pCE8PFdP2kJLLzsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: oB0NKnggttEU6xDAEk5ryX1HyzQ_ake6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_01,2026-03-16_06,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170065 On 3/17/2026 3:22 PM, Can Guo wrote: > Hi Peter, > > On 3/17/2026 2:49 PM, Peter Wang (王信友) wrote: >> >> On Sun, 2026-03-08 at 08:14 -0700, Can Guo wrote: >> > +static bool use_txeq_presets = true; >> >> Hi Can, >> >> The default should scan all, not only presets. >> Or, how could make sure the best FOM is in the presets? > Here is the consideration: > > 1. Scanning all 64 PreShoot/DeEmphasis combinations cost (much) more time >   a. This could impact bootup KPI >   b. During TX EQTR, IOs are paused, when one conducts a re-training, > the IOs could >        be paused for too long. > 2. As per our study in the past few months, the optimal/best > combination is most >     likely within the 8 presets, which is true for both Host TX lanes > and Device TX lanes. > 3. Even if sometime the optimal settings which fall out of the 8 > presets, they are very >     close to optimal one found within the 8 presets. > > So, scanning the 8 presets only is more cost-efficient. >> >> > +ufshcd_tx_eqtr_result_examine(struct ufshcd_tx_eq_params >> > *old_params, >> > +                             struct ufshcd_tx_eq_params *new_params) >> > +{ >> > +       int lane; >> > + >> > +       if (!old_params->is_valid) >> > +               return; >> >> Is is_valid always false, causing a return here? > It can be valid if we are here (again) because one conducts a > re-training. >> >> >> > > +                       /* Step 3 - Apply TX EQTR settings */ >> > +                       ret = ufshcd_apply_tx_eqtr_settings(hba, >> > pwr_mode, &h_iter, &d_iter); >> > +                       if (ret) { >> > +                               dev_err(hba->dev, "Failed to apply TX >> > EQTR settings: %d\n", >> > +                                       ret); >> >> Can deemphasis and preshoot be printed as well? > Sure. >> >> >> > +       ret = ufshcd_vops_tx_eqtr_notify(hba, POST_CHANGE, pwr_mode); >> > +       if (ret) >> > +               goto out; >> > + >> > +out: >> > >> The if check can be removed. > Good catch. >> >> >> >> > + * @is_new: Flag to indicate whether re-newed since previous >> > iteration >> >> is_new is confusing to me. Please consider using "need_renew" or >> "update_required", which are clearer. > I will move to 'is_updated'. >> >> >> > +struct ufshcd_tx_eq_params { >> > +       u32 tx_lanes; >> > +       u32 rx_lanes; >> > + >> > +       struct ufshcd_tx_eq_settings host[PA_MAXDATALANES]; >> > +       struct ufshcd_tx_eq_settings device[PA_MAXDATALANES]; >> > + >> > +       u32 >> > host_eqtr_record[PA_MAXDATALANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMP >> > HASIS]; >> > +       u32 >> > device_eqtr_record[PA_MAXDATALANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEE >> > MPHASIS]; >> > >> Do these two records only store the FOM and are not used otherwise? > They are used by debugfs entries to print out the TX EQTR history. >> >> > + >> > +       ktime_t last_eqtr_ts; >> > +       int num_eqtr_records; >> > + >> > +       u32 saved_adapt_eqtr; >> > + >> > +       bool is_valid; >> > +       bool is_applied; >> > +}; >> >> The size of the struct ufshcd_tx_eq_params is 2.2K. >> It seems that some fields could use u8 instead of u32. >> >> >> > +       struct ufshcd_tx_eq_params tx_eq_params[UFS_HS_GEAR_MAX - 1]; >> >> This uses up to 12KB of memory. Is it really necessary to occupy >> so much memory? Can we use dynamic memory allocation instead? >> Especially since G1/G2/G3 are not used, and G4/G5 are optional. >> Only G6 is actually needed, so we shouldn't waste so much memory. >> After all, memory is expensive nowadays. > 1. Even we use dynamic memory, it is still the same amount of memory. > 2. G1/G2/G3 supports also TX Equalization settings, my next series > will provide >     changes to allow one to give TX Equalization settings from DTS and/or >     persistent memory. > 3. G4/G5 supports TX Equalization as well as TX Equalization training > as per >     spec, we should support them like G6 equally to enable better link > quality. The main data struct which is costing memory is the TX EQTR record arrays, I can optimize in next very by dynamically allocating memory ONLY for the Gears which actually need TX EQTR. Thanks, Can Guo. >> >> >> > +#define PA_PEERRXHSG6ADAPTINITIALL0L3          0x15DF >> > +#define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3      0x15DE >> > >> These two lines should be swapped to match the correct order. > Will do. > > Thanks, > Can Guo. >> >> Thanks >> Peter >> >> >> ************* MEDIATEK Confidentiality Notice >>   ******************** >> The information contained in this e-mail message (including any >> attachments) may be confidential, proprietary, privileged, or otherwise >> exempt from disclosure under applicable laws. It is intended to be >> conveyed only to the designated recipient(s). Any use, dissemination, >> distribution, printing, retaining or copying of this e-mail >> (including its >> attachments) by unintended recipient(s) is strictly prohibited and may >> be unlawful. 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