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([2800:a4:806:ef00:2f77:7097:372d:6d14]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67c58a294ffsm3158931d50.23.2026.11.10.15.56.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 15:56:19 -0800 (PST) Message-ID: Date: Tue, 10 Nov 2026 23:56:13 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/7] phy: qcom-mipi-csi2: Add SM8150 CSI2 DPHY support To: Bryan O'Donoghue , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Andi Shyti , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org References: <20261106-sm8150-v7.4-rc1-camss-v3-0-0103e8a0bbcd@andrewgigena.dev> <20261106-sm8150-v7.4-rc1-camss-v3-6-0103e8a0bbcd@andrewgigena.dev> <88407f72-0c6e-4e46-b97b-7031c237dac7@kernel.org> <83c6281f-1887-4481-8c63-957b4bc856b9@linaro.org> Content-Language: en-US From: Andrew Gigena In-Reply-To: <83c6281f-1887-4481-8c63-957b4bc856b9@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Bryan, > What you could do to unblock your series and not have a dependency on > another series is cherry-pick the necessary patch. > > https://patchwork.linuxtv.org/project/linux-media/patch/20261102213936.1251316-1-anusha.nandi@oss.qualcomm.com/ I took Anusha's approach and dropped the dev_pm_domain_detach() hack. Single power-domain SoCs now use dev_pm_domain_attach(dev, 0) and the loops check for a NULL pd_list. I folded it into the PHY patch with Co-developed-by and Signed-off-by for Anusha, so the series has no dependency on another series. On your other points: > Is there really no AHB clock to be listed here ? Seems again suspect. There is no separate AHB clock. The "core" clock is cam_cc_csiphyN_clk, whose parent is cam_cc_cphy_rx_clk_src at 400 MHz, and the second clock is the CSI PHY timer. > These are not the correct names Renamed to vdda-0p9 and vdda-1p2 in the binding, the driver and the DTS. > But why ? The SM8150 timer RCG only has 19.2 MHz and 300 MHz. link_freq / 4 rounds down to 19.2 MHz and the settle count comes out zero, so the rate is pinned to 300 MHz through timer_rate_hz. Best regards, Andrew