From: David Woodhouse <dwmw2@infradead.org>
To: Christoph Hellwig <hch@infradead.org>
Cc: virtio-comment@lists.linux.dev, mst@redhat.com,
"Claire Chang" <tientzu@chromium.org>,
linux-devicetree <devicetree@vger.kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Jörg Roedel" <joro@8bytes.org>,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
graf@amazon.de
Subject: Re: [RFC PATCH 1/3] content: Add VIRTIO_F_SWIOTLB to negotiate use of SWIOTLB bounce buffers
Date: Fri, 04 Apr 2025 08:50:47 +0100 [thread overview]
Message-ID: <fb7ea3ee5bf970fa36b012e16750f533b72903a0.camel@infradead.org> (raw)
In-Reply-To: <Z-99snVF5ESyJDDs@infradead.org>
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On Thu, 2025-04-03 at 23:35 -0700, Christoph Hellwig wrote:
> As stated above I suspect you still are asking the wrong question and
> have the wrong mental model. Virtio fundamentally can do DMA, you just
> don't want it to. And based on the other subthread I also suspect you'd
> actually be much better off with your bounce buffer in the virtual host
> memory instead of coming up with this particularly odd case, but even
> if not it's the system description that matters here, not the device
> model.
I do agree, this is fundamentally a system issue. In a CoCo model, it's
non-trivial for the system to allow *virtual* devices to do "DMA"
because that actually means allowing the VMM to access arbitrary guest
memory.
And most hardware designers screwed up the 2-stage IOMMU which allows
protection from *real* devices, and didn't build in a way for the VMM
to access guest memory through a stage1 mapping.
Fixing that to allow system DMA to those guest devices in a way which
will work across operating systems is impractical, as it involves the
guest knowing which PCI device is implemented where, and either core
kernel (share/unshare) enlightenments, or emulating a full IOMMU in the
*trusted* part of the hypervisor (e.g. pKVM).
So "for the emulated devices, just use a device model that doesn't do
arbitrary DMA to system memory" is a nice simple answer, and keeps the
guest support restricted to its *own* standalone driver.
And yes, virtio is kind of fundamentally DMA-based as you said, but
that's OK if the DMA is only to a specific range which is *known* to be
shareable and which the guest would never consider to be 'normal RAM'.
Because then the VMM can be *allowed* to access that.
What's annoying is that this should work out of the box *already* with
virtio-mmio and a `restricted-dma-pool` — for systems which aren't
afflicted by UEFI/ACPI/PCI as their discovery mechanisms.
In fact, I may even try offering virtio-mmio in a PRP0001 ACPI device
to see how that works, although I think I'll lament the lack of MSI
interrupts.
But the cleaner solution seemed (at least when I started this
discussion) to be to add the same kind of facility to the virtio-pci
transport too. And I still don't think I've quite given up on it;
especially as you point out the use case for staged P2P DMA too.
I'll go take a closer look at how we can cleanly disambiguate between
address spaces.
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next prev parent reply other threads:[~2025-04-04 7:50 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-02 11:04 [RFC PATCH 0/3] Add Software IOTLB bounce buffer support David Woodhouse
2025-04-02 11:04 ` [RFC PATCH 1/3] content: Add VIRTIO_F_SWIOTLB to negotiate use of SWIOTLB bounce buffers David Woodhouse
2025-04-02 14:54 ` Michael S. Tsirkin
2025-04-02 15:12 ` David Woodhouse
2025-04-02 15:20 ` Michael S. Tsirkin
2025-04-02 15:47 ` David Woodhouse
2025-04-02 15:51 ` Michael S. Tsirkin
2025-04-02 16:16 ` David Woodhouse
2025-04-02 16:43 ` Michael S. Tsirkin
2025-04-02 17:10 ` David Woodhouse
2025-04-03 7:29 ` Christoph Hellwig
2025-04-03 7:37 ` David Woodhouse
2025-04-03 7:39 ` Christoph Hellwig
2025-04-03 7:43 ` Michael S. Tsirkin
2025-04-03 7:44 ` Christoph Hellwig
2025-04-03 8:10 ` David Woodhouse
2025-04-04 6:29 ` Christoph Hellwig
2025-04-04 6:39 ` David Woodhouse
2025-04-04 6:44 ` Christoph Hellwig
2025-04-04 6:45 ` Christoph Hellwig
2025-04-03 7:41 ` Michael S. Tsirkin
2025-04-03 7:31 ` Michael S. Tsirkin
2025-04-03 7:45 ` David Woodhouse
2025-04-03 8:06 ` Michael S. Tsirkin
2025-04-03 7:13 ` Zhu Lingshan
2025-04-03 7:24 ` David Woodhouse
2025-04-03 7:31 ` Zhu Lingshan
2025-04-04 10:27 ` David Woodhouse
2025-04-03 7:34 ` Michael S. Tsirkin
2025-04-03 7:54 ` David Woodhouse
2025-04-03 8:13 ` Michael S. Tsirkin
2025-04-03 8:22 ` David Woodhouse
2025-04-03 8:34 ` Zhu Lingshan
2025-04-03 8:57 ` David Woodhouse
2025-04-06 6:23 ` Zhu Lingshan
2025-04-03 13:19 ` Michael S. Tsirkin
2025-04-03 7:24 ` Christoph Hellwig
2025-04-03 7:28 ` David Woodhouse
2025-04-03 7:35 ` Christoph Hellwig
2025-04-03 8:06 ` David Woodhouse
2025-04-04 6:35 ` Christoph Hellwig
2025-04-04 7:50 ` David Woodhouse [this message]
2025-04-04 8:09 ` Michael S. Tsirkin
2025-04-04 8:16 ` David Woodhouse
2025-04-04 8:32 ` Michael S. Tsirkin
2025-04-04 9:27 ` David Woodhouse
2025-04-04 10:15 ` David Woodhouse
2025-04-04 10:37 ` Michael S. Tsirkin
2025-04-04 11:15 ` David Woodhouse
2025-04-06 18:28 ` Michael S. Tsirkin
2025-04-06 18:47 ` David Woodhouse
2025-04-07 7:30 ` Christoph Hellwig
2025-04-07 7:54 ` David Woodhouse
2025-04-07 9:05 ` Christoph Hellwig
2025-04-07 10:09 ` David Woodhouse
2025-04-07 14:06 ` Christoph Hellwig
2025-04-07 14:59 ` David Woodhouse
2025-04-07 12:14 ` Michael S. Tsirkin
2025-04-07 12:46 ` David Woodhouse
2025-04-07 7:26 ` Christoph Hellwig
2025-04-07 7:23 ` Christoph Hellwig
2025-04-07 7:19 ` Christoph Hellwig
2025-04-04 8:23 ` Christoph Hellwig
2025-04-04 9:39 ` David Woodhouse
2025-04-07 7:34 ` Christoph Hellwig
2025-04-07 9:40 ` David Woodhouse
2025-04-02 11:04 ` [RFC PATCH 2/3] transport-mmio: Document restricted-dma-pool SWIOTLB bounce buffer David Woodhouse
2025-04-02 11:04 ` [RFC PATCH 3/3] transport-pci: Add SWIOTLB bounce buffer capability David Woodhouse
2025-04-02 14:58 ` Michael S. Tsirkin
2025-04-02 15:21 ` David Woodhouse
2025-04-03 7:27 ` Michael S. Tsirkin
2025-04-03 7:36 ` Zhu Lingshan
2025-04-03 7:37 ` Michael S. Tsirkin
2025-04-03 8:12 ` Zhu Lingshan
2025-04-03 8:16 ` Michael S. Tsirkin
2025-04-03 8:37 ` Zhu Lingshan
2025-04-03 8:44 ` David Woodhouse
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