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Aug 2024 16:55:46 +0000 Received: from LO4P123MB5272.GBRP123.PROD.OUTLOOK.COM ([fe80::55a9:7dae:8812:f567]) by LO4P123MB5272.GBRP123.PROD.OUTLOOK.COM ([fe80::55a9:7dae:8812:f567%5]) with mapi id 15.20.7897.014; Fri, 23 Aug 2024 16:55:46 +0000 Message-ID: Date: Fri, 23 Aug 2024 18:55:44 +0200 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 3/3] serial: sc16is7xx: convert bitmask definitions to use BIT() macro From: Lech Perczak To: linux-serial@vger.kernel.org, "linux-kernel@vger.kernel.org" Cc: Greg Kroah-Hartman , Jiri Slaby , Hugo Villeneuve , Andy Shevchenko , =?UTF-8?Q?Krzysztof_Drobi=C5=84ski?= , =?UTF-8?Q?Pawe=C5=82_Lenkow?= , Kirill Yatsenko References: <7deb753f-bf86-47ce-89bf-8277aca4293e@camlingroup.com> In-Reply-To: <7deb753f-bf86-47ce-89bf-8277aca4293e@camlingroup.com> X-ClientProxiedBy: WA2P291CA0005.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:1e::11) To LO4P123MB5272.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:20b::7) Precedence: bulk X-Mailing-List: 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cd508958-bac7-44a4-5c6a-08dcc3946f0c X-MS-Exchange-CrossTenant-AuthSource: LO4P123MB5272.GBRP123.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2024 16:55:46.6344 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: fd4b1729-b18d-46d2-9ba0-2717b852b252 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: De2EjTdwDXj5e91WxLP/BuV8TGI4i8/4l6BcBexfWNA0p0wEF71WixavQh1sm6DskR2AIfwDDcnuops6kpUOm5qxpCGqx8mohbXt0+S0OYI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CWLP123MB3105 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: camlingroup.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Now that bit definition comments were cleaned up, convert bitmask definitions to use BIT() macro for clarity. Convert SC16IS7XX_IIR_* bitmask constants, to use GENMASK() macro, where applicable - while at that, realign comments. Compose SC16IS7XX_LSR_BRK_ERROR_MASK using aforementioned constants, instead of open-coding it, and remove now unneeded comment. Signed-off-by: Lech Perczak --- Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Hugo Villeneuve Cc: Andy Shevchenko --- drivers/tty/serial/sc16is7xx.c | 174 +++++++++++++++++---------------- 1 file changed, 89 insertions(+), 85 deletions(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.= c index 36b7c682ae94..68fdb2dee414 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -10,6 +10,7 @@ #undef DEFAULT_SYMBOL_NAMESPACE #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX =20 +#include #include #include #include @@ -77,52 +78,52 @@ #define SC16IS7XX_XOFF2_REG=09=09(0x07) /* Xoff2 word */ =20 /* IER register bits */ -#define SC16IS7XX_IER_RDI_BIT=09=09(1 << 0) /* Enable RX data interrupt */ -#define SC16IS7XX_IER_THRI_BIT=09=09(1 << 1) /* Enable TX holding register +#define SC16IS7XX_IER_RDI_BIT=09=09BIT(0) /* Enable RX data interrupt */ +#define SC16IS7XX_IER_THRI_BIT=09=09BIT(1) /* Enable TX holding register =09=09=09=09=09=09 * interrupt */ -#define SC16IS7XX_IER_RLSI_BIT=09=09(1 << 2) /* Enable RX line status +#define SC16IS7XX_IER_RLSI_BIT=09=09BIT(2) /* Enable RX line status =09=09=09=09=09=09 * interrupt */ -#define SC16IS7XX_IER_MSI_BIT=09=09(1 << 3) /* Enable Modem status +#define SC16IS7XX_IER_MSI_BIT=09=09BIT(3) /* Enable Modem status =09=09=09=09=09=09 * interrupt */ =20 /* IER register bits - write only if (EFR[4] =3D=3D 1) */ -#define SC16IS7XX_IER_SLEEP_BIT=09=09(1 << 4) /* Enable Sleep mode */ -#define SC16IS7XX_IER_XOFFI_BIT=09=09(1 << 5) /* Enable Xoff interrupt */ -#define SC16IS7XX_IER_RTSI_BIT=09=09(1 << 6) /* Enable nRTS interrupt */ -#define SC16IS7XX_IER_CTSI_BIT=09=09(1 << 7) /* Enable nCTS interrupt */ +#define SC16IS7XX_IER_SLEEP_BIT=09=09BIT(4) /* Enable Sleep mode */ +#define SC16IS7XX_IER_XOFFI_BIT=09=09BIT(5) /* Enable Xoff interrupt */ +#define SC16IS7XX_IER_RTSI_BIT=09=09BIT(6) /* Enable nRTS interrupt */ +#define SC16IS7XX_IER_CTSI_BIT=09=09BIT(7) /* Enable nCTS interrupt */ =20 /* FCR register bits */ -#define SC16IS7XX_FCR_FIFO_BIT=09=09(1 << 0) /* Enable FIFO */ -#define SC16IS7XX_FCR_RXRESET_BIT=09(1 << 1) /* Reset RX FIFO */ -#define SC16IS7XX_FCR_TXRESET_BIT=09(1 << 2) /* Reset TX FIFO */ -#define SC16IS7XX_FCR_RXLVLL_BIT=09(1 << 6) /* RX Trigger level LSB */ -#define SC16IS7XX_FCR_RXLVLH_BIT=09(1 << 7) /* RX Trigger level MSB */ +#define SC16IS7XX_FCR_FIFO_BIT=09=09BIT(0) /* Enable FIFO */ +#define SC16IS7XX_FCR_RXRESET_BIT=09BIT(1) /* Reset RX FIFO */ +#define SC16IS7XX_FCR_TXRESET_BIT=09BIT(2) /* Reset TX FIFO */ +#define SC16IS7XX_FCR_RXLVLL_BIT=09BIT(6) /* RX Trigger level LSB */ +#define SC16IS7XX_FCR_RXLVLH_BIT=09BIT(7) /* RX Trigger level MSB */ =20 /* FCR register bits - write only if (EFR[4] =3D=3D 1) */ -#define SC16IS7XX_FCR_TXLVLL_BIT=09(1 << 4) /* TX Trigger level LSB */ -#define SC16IS7XX_FCR_TXLVLH_BIT=09(1 << 5) /* TX Trigger level MSB */ +#define SC16IS7XX_FCR_TXLVLL_BIT=09BIT(4) /* TX Trigger level LSB */ +#define SC16IS7XX_FCR_TXLVLH_BIT=09BIT(5) /* TX Trigger level MSB */ =20 /* IIR register bits */ -#define SC16IS7XX_IIR_NO_INT_BIT=09(1 << 0) /* No interrupts pending */ -#define SC16IS7XX_IIR_ID_MASK=09=090x3e /* Mask for the interrupt ID *= / -#define SC16IS7XX_IIR_THRI_SRC=09=090x02 /* TX holding register empty = */ -#define SC16IS7XX_IIR_RDI_SRC=09=090x04 /* RX data interrupt */ -#define SC16IS7XX_IIR_RLSE_SRC=09=090x06 /* RX line status error */ -#define SC16IS7XX_IIR_RTOI_SRC=09=090x0c /* RX time-out interrupt */ -#define SC16IS7XX_IIR_MSI_SRC=09=090x00 /* Modem status interrupt -=09=09=09=09=09=09 * - only on 75x/76x -=09=09=09=09=09=09 */ -#define SC16IS7XX_IIR_INPIN_SRC=09=090x30 /* Input pin change of state -=09=09=09=09=09=09 * - only on 75x/76x -=09=09=09=09=09=09 */ -#define SC16IS7XX_IIR_XOFFI_SRC=09=090x10 /* Received Xoff */ -#define SC16IS7XX_IIR_CTSRTS_SRC=090x20 /* nCTS,nRTS change of state -=09=09=09=09=09=09 * from active (LOW) -=09=09=09=09=09=09 * to inactive (HIGH) -=09=09=09=09=09=09 */ +#define SC16IS7XX_IIR_NO_INT_BIT=09BIT(0) =09/* No interrupts pending */ +#define SC16IS7XX_IIR_ID_MASK=09=09GENMASK(5,1)=09/* Mask for the interrup= t ID */ +#define SC16IS7XX_IIR_THRI_SRC=09=09BIT(1)=09=09/* TX holding register emp= ty */ +#define SC16IS7XX_IIR_RDI_SRC=09=09BIT(2)=09=09/* RX data interrupt */ +#define SC16IS7XX_IIR_RLSE_SRC=09=09GENMASK(2,1)=09/* RX line status error= */ +#define SC16IS7XX_IIR_RTOI_SRC=09=09GENMASK(3,2) /* RX time-out interru= pt */ +#define SC16IS7XX_IIR_MSI_SRC=09=090x00=09=09/* Modem status interrupt +=09=09=09=09=09=09=09 * - only on 75x/76x +=09=09=09=09=09=09=09 */ +#define SC16IS7XX_IIR_INPIN_SRC=09=09GENMASK(5,4)=09/* Input pin change of= state +=09=09=09=09=09=09=09 * - only on 75x/76x +=09=09=09=09=09=09=09 */ +#define SC16IS7XX_IIR_XOFFI_SRC=09=09BIT(4)=09=09/* Received Xoff */ +#define SC16IS7XX_IIR_CTSRTS_SRC=09BIT(5)=09=09/* nCTS,nRTS change of stat= e +=09=09=09=09=09=09=09 * from active (LOW) +=09=09=09=09=09=09=09 * to inactive (HIGH) +=09=09=09=09=09=09=09 */ /* LCR register bits */ -#define SC16IS7XX_LCR_LENGTH0_BIT=09(1 << 0) /* Word length bit 0 */ -#define SC16IS7XX_LCR_LENGTH1_BIT=09(1 << 1) /* Word length bit 1 +#define SC16IS7XX_LCR_LENGTH0_BIT=09BIT(0) /* Word length bit 0 */ +#define SC16IS7XX_LCR_LENGTH1_BIT=09BIT(1) /* Word length bit 1 =09=09=09=09=09=09 * =09=09=09=09=09=09 * Word length bits table: =09=09=09=09=09=09 * 00 -> 5 bit words @@ -130,7 +131,7 @@ =09=09=09=09=09=09 * 10 -> 7 bit words =09=09=09=09=09=09 * 11 -> 8 bit words =09=09=09=09=09=09 */ -#define SC16IS7XX_LCR_STOPLEN_BIT=09(1 << 2) /* STOP length bit +#define SC16IS7XX_LCR_STOPLEN_BIT=09BIT(2) /* STOP length bit =09=09=09=09=09=09 * =09=09=09=09=09=09 * STOP length bit table: =09=09=09=09=09=09 * 0 -> 1 stop bit @@ -138,11 +139,11 @@ =09=09=09=09=09=09 * word length is 5, =09=09=09=09=09=09 * 2 stop bits otherwise =09=09=09=09=09=09 */ -#define SC16IS7XX_LCR_PARITY_BIT=09(1 << 3) /* Parity bit enable */ -#define SC16IS7XX_LCR_EVENPARITY_BIT=09(1 << 4) /* Even parity bit enable = */ -#define SC16IS7XX_LCR_FORCEPARITY_BIT=09(1 << 5) /* 9-bit multidrop parity= */ -#define SC16IS7XX_LCR_TXBREAK_BIT=09(1 << 6) /* TX break enable */ -#define SC16IS7XX_LCR_DLAB_BIT=09=09(1 << 7) /* Divisor Latch enable */ +#define SC16IS7XX_LCR_PARITY_BIT=09BIT(3) /* Parity bit enable */ +#define SC16IS7XX_LCR_EVENPARITY_BIT=09BIT(4) /* Even parity bit enable = */ +#define SC16IS7XX_LCR_FORCEPARITY_BIT=09BIT(5) /* 9-bit multidrop parity= */ +#define SC16IS7XX_LCR_TXBREAK_BIT=09BIT(6) /* TX break enable */ +#define SC16IS7XX_LCR_DLAB_BIT=09=09BIT(7) /* Divisor Latch enable */ #define SC16IS7XX_LCR_WORD_LEN_5=09(0x00) #define SC16IS7XX_LCR_WORD_LEN_6=09(0x01) #define SC16IS7XX_LCR_WORD_LEN_7=09(0x02) @@ -153,58 +154,61 @@ =09=09=09=09=09=09=09=09* reg set */ =20 /* MCR register bits */ -#define SC16IS7XX_MCR_DTR_BIT=09=09(1 << 0) /* DTR complement +#define SC16IS7XX_MCR_DTR_BIT=09=09BIT(0) /* DTR complement =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ -#define SC16IS7XX_MCR_RTS_BIT=09=09(1 << 1) /* RTS complement */ -#define SC16IS7XX_MCR_TCRTLR_BIT=09(1 << 2) /* TCR/TLR register enable */ -#define SC16IS7XX_MCR_LOOP_BIT=09=09(1 << 4) /* Enable loopback test mode = */ -#define SC16IS7XX_MCR_XONANY_BIT=09(1 << 5) /* Enable Xon Any +#define SC16IS7XX_MCR_RTS_BIT=09=09BIT(1) /* RTS complement */ +#define SC16IS7XX_MCR_TCRTLR_BIT=09BIT(2) /* TCR/TLR register enable */ +#define SC16IS7XX_MCR_LOOP_BIT=09=09BIT(4) /* Enable loopback test mode = */ +#define SC16IS7XX_MCR_XONANY_BIT=09BIT(5) /* Enable Xon Any =09=09=09=09=09=09 * - write enabled =09=09=09=09=09=09 * if (EFR[4] =3D=3D 1) =09=09=09=09=09=09 */ -#define SC16IS7XX_MCR_IRDA_BIT=09=09(1 << 6) /* Enable IrDA mode +#define SC16IS7XX_MCR_IRDA_BIT=09=09BIT(6) /* Enable IrDA mode =09=09=09=09=09=09 * - write enabled =09=09=09=09=09=09 * if (EFR[4] =3D=3D 1) =09=09=09=09=09=09 */ -#define SC16IS7XX_MCR_CLKSEL_BIT=09(1 << 7) /* Divide clock by 4 +#define SC16IS7XX_MCR_CLKSEL_BIT=09BIT(7) /* Divide clock by 4 =09=09=09=09=09=09 * - write enabled =09=09=09=09=09=09 * if (EFR[4] =3D=3D 1) =09=09=09=09=09=09 */ =20 /* LSR register bits */ -#define SC16IS7XX_LSR_DR_BIT=09=09(1 << 0) /* Receiver data ready */ -#define SC16IS7XX_LSR_OE_BIT=09=09(1 << 1) /* Overrun Error */ -#define SC16IS7XX_LSR_PE_BIT=09=09(1 << 2) /* Parity Error */ -#define SC16IS7XX_LSR_FE_BIT=09=09(1 << 3) /* Frame Error */ -#define SC16IS7XX_LSR_BI_BIT=09=09(1 << 4) /* Break Interrupt */ -#define SC16IS7XX_LSR_BRK_ERROR_MASK=090x1E /* BI, FE, PE, OE bits */ -#define SC16IS7XX_LSR_THRE_BIT=09=09(1 << 5) /* TX holding register empty = */ -#define SC16IS7XX_LSR_TEMT_BIT=09=09(1 << 6) /* Transmitter empty */ -#define SC16IS7XX_LSR_FIFOE_BIT=09=09(1 << 7) /* Fifo Error */ +#define SC16IS7XX_LSR_DR_BIT=09=09BIT(0) /* Receiver data ready */ +#define SC16IS7XX_LSR_OE_BIT=09=09BIT(1) /* Overrun Error */ +#define SC16IS7XX_LSR_PE_BIT=09=09BIT(2) /* Parity Error */ +#define SC16IS7XX_LSR_FE_BIT=09=09BIT(3) /* Frame Error */ +#define SC16IS7XX_LSR_BI_BIT=09=09BIT(4) /* Break Interrupt */ +#define SC16IS7XX_LSR_BRK_ERROR_MASK=09(SC16IS7XX_LSR_OE_BIT | \ +=09=09=09=09=09SC16IS7XX_LSR_PE_BIT | \ +=09=09=09=09=09SC16IS7XX_LSR_FE_BIT | \ +=09=09=09=09=09SC16IS7XX_LSR_BI_BIT) +#define SC16IS7XX_LSR_THRE_BIT=09=09BIT(5) /* TX holding register empty = */ +#define SC16IS7XX_LSR_TEMT_BIT=09=09BIT(6) /* Transmitter empty */ +#define SC16IS7XX_LSR_FIFOE_BIT=09=09BIT(7) /* Fifo Error */ =20 /* MSR register bits */ -#define SC16IS7XX_MSR_DCTS_BIT=09=09(1 << 0) /* Delta CTS Clear To Send */ -#define SC16IS7XX_MSR_DDSR_BIT=09=09(1 << 1) /* Delta DSR Data Set Ready +#define SC16IS7XX_MSR_DCTS_BIT=09=09BIT(0) /* Delta CTS Clear To Send */ +#define SC16IS7XX_MSR_DDSR_BIT=09=09BIT(1) /* Delta DSR Data Set Ready =09=09=09=09=09=09 * or (IO4) =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ -#define SC16IS7XX_MSR_DRI_BIT=09=09(1 << 2) /* Delta RI Ring Indicator +#define SC16IS7XX_MSR_DRI_BIT=09=09BIT(2) /* Delta RI Ring Indicator =09=09=09=09=09=09 * or (IO7) =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ -#define SC16IS7XX_MSR_DCD_BIT=09=09(1 << 3) /* Delta CD Carrier Detect +#define SC16IS7XX_MSR_DCD_BIT=09=09BIT(3) /* Delta CD Carrier Detect =09=09=09=09=09=09 * or (IO6) =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ -#define SC16IS7XX_MSR_CTS_BIT=09=09(1 << 4) /* CTS */ -#define SC16IS7XX_MSR_DSR_BIT=09=09(1 << 5) /* DSR (IO4) +#define SC16IS7XX_MSR_CTS_BIT=09=09BIT(4) /* CTS */ +#define SC16IS7XX_MSR_DSR_BIT=09=09BIT(5) /* DSR (IO4) =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ -#define SC16IS7XX_MSR_RI_BIT=09=09(1 << 6) /* RI (IO7) +#define SC16IS7XX_MSR_RI_BIT=09=09BIT(6) /* RI (IO7) =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ -#define SC16IS7XX_MSR_CD_BIT=09=09(1 << 7) /* CD (IO6) +#define SC16IS7XX_MSR_CD_BIT=09=09BIT(7) /* CD (IO6) =09=09=09=09=09=09 * - only on 75x/76x =09=09=09=09=09=09 */ =20 @@ -239,19 +243,19 @@ #define SC16IS7XX_TLR_RX_TRIGGER(words)=09((((words) / 4) & 0x0f) << 4) =20 /* IOControl register bits (Only 75x/76x) */ -#define SC16IS7XX_IOCONTROL_LATCH_BIT=09(1 << 0) /* Enable input latching = */ -#define SC16IS7XX_IOCONTROL_MODEM_A_BIT=09(1 << 1) /* Enable GPIO[7:4] as = modem A pins */ -#define SC16IS7XX_IOCONTROL_MODEM_B_BIT=09(1 << 2) /* Enable GPIO[3:0] as = modem B pins */ -#define SC16IS7XX_IOCONTROL_SRESET_BIT=09(1 << 3) /* Software Reset */ +#define SC16IS7XX_IOCONTROL_LATCH_BIT=09BIT(0) /* Enable input latching = */ +#define SC16IS7XX_IOCONTROL_MODEM_A_BIT=09BIT(1) /* Enable GPIO[7:4] as = modem A pins */ +#define SC16IS7XX_IOCONTROL_MODEM_B_BIT=09BIT(2) /* Enable GPIO[3:0] as = modem B pins */ +#define SC16IS7XX_IOCONTROL_SRESET_BIT=09BIT(3) /* Software Reset */ =20 /* EFCR register bits */ -#define SC16IS7XX_EFCR_9BIT_MODE_BIT=09(1 << 0) /* Enable 9-bit or Multidr= op +#define SC16IS7XX_EFCR_9BIT_MODE_BIT=09BIT(0) /* Enable 9-bit or Multidr= op =09=09=09=09=09=09 * mode (RS485) */ -#define SC16IS7XX_EFCR_RXDISABLE_BIT=09(1 << 1) /* Disable receiver */ -#define SC16IS7XX_EFCR_TXDISABLE_BIT=09(1 << 2) /* Disable transmitter */ -#define SC16IS7XX_EFCR_AUTO_RS485_BIT=09(1 << 4) /* Auto RS485 RTS directi= on */ -#define SC16IS7XX_EFCR_RTS_INVERT_BIT=09(1 << 5) /* RTS output inversion *= / -#define SC16IS7XX_EFCR_IRDA_MODE_BIT=09(1 << 7) /* IrDA mode +#define SC16IS7XX_EFCR_RXDISABLE_BIT=09BIT(1) /* Disable receiver */ +#define SC16IS7XX_EFCR_TXDISABLE_BIT=09BIT(2) /* Disable transmitter */ +#define SC16IS7XX_EFCR_AUTO_RS485_BIT=09BIT(4) /* Auto RS485 RTS directi= on */ +#define SC16IS7XX_EFCR_RTS_INVERT_BIT=09BIT(5) /* RTS output inversion *= / +#define SC16IS7XX_EFCR_IRDA_MODE_BIT=09BIT(7) /* IrDA mode =09=09=09=09=09=09 * 0 =3D rate upto 115.2 kbit/s =09=09=09=09=09=09 * - Only 75x/76x =09=09=09=09=09=09 * 1 =3D rate upto 1.152 Mbit/s @@ -259,15 +263,15 @@ =09=09=09=09=09=09 */ =20 /* EFR register bits */ -#define SC16IS7XX_EFR_AUTORTS_BIT=09(1 << 6) /* Auto RTS flow ctrl enable = */ -#define SC16IS7XX_EFR_AUTOCTS_BIT=09(1 << 7) /* Auto CTS flow ctrl enable = */ -#define SC16IS7XX_EFR_XOFF2_DETECT_BIT=09(1 << 5) /* Enable Xoff2 detectio= n */ -#define SC16IS7XX_EFR_ENABLE_BIT=09(1 << 4) /* Enable enhanced functions +#define SC16IS7XX_EFR_AUTORTS_BIT=09BIT(6) /* Auto RTS flow ctrl enable = */ +#define SC16IS7XX_EFR_AUTOCTS_BIT=09BIT(7) /* Auto CTS flow ctrl enable = */ +#define SC16IS7XX_EFR_XOFF2_DETECT_BIT=09BIT(5) /* Enable Xoff2 detectio= n */ +#define SC16IS7XX_EFR_ENABLE_BIT=09BIT(4) /* Enable enhanced functions =09=09=09=09=09=09 * and writing to IER[7:4], =09=09=09=09=09=09 * FCR[5:4], MCR[7:5] =09=09=09=09=09=09 */ -#define SC16IS7XX_EFR_SWFLOW3_BIT=09(1 << 3) -#define SC16IS7XX_EFR_SWFLOW2_BIT=09(1 << 2) +#define SC16IS7XX_EFR_SWFLOW3_BIT=09BIT(3) +#define SC16IS7XX_EFR_SWFLOW2_BIT=09BIT(2) =09=09=09=09=09=09 /* =09=09=09=09=09=09 * SWFLOW bits 3 & 2 table: =09=09=09=09=09=09 * 00 -> no transmitter flow @@ -280,8 +284,8 @@ =09=09=09=09=09=09 * XON1, XON2, XOFF1 and =09=09=09=09=09=09 * XOFF2 =09=09=09=09=09=09 */ -#define SC16IS7XX_EFR_SWFLOW1_BIT=09(1 << 1) -#define SC16IS7XX_EFR_SWFLOW0_BIT=09(1 << 0) +#define SC16IS7XX_EFR_SWFLOW1_BIT=09BIT(1) +#define SC16IS7XX_EFR_SWFLOW0_BIT=09BIT(0) =09=09=09=09=09=09 /* =09=09=09=09=09=09 * SWFLOW bits 1 & 0 table: =09=09=09=09=09=09 * 00 -> no received flow @@ -307,9 +311,9 @@ #define SC16IS7XX_FIFO_SIZE=09=09(64) #define SC16IS7XX_GPIOS_PER_BANK=094 =20 -#define SC16IS7XX_RECONF_MD=09=09(1 << 0) -#define SC16IS7XX_RECONF_IER=09=09(1 << 1) -#define SC16IS7XX_RECONF_RS485=09=09(1 << 2) +#define SC16IS7XX_RECONF_MD=09=09BIT(0) +#define SC16IS7XX_RECONF_IER=09=09BIT(1) +#define SC16IS7XX_RECONF_RS485=09=09BIT(2) =20 struct sc16is7xx_one_config { =09unsigned int=09=09=09flags; --=20 2.34.1