From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 065C46ADD; Sun, 3 Aug 2025 08:17:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754209048; cv=none; b=uO9kV0oCOeqbyRjHpYu9ibXKx48Dvl3ap8lKaZReipocBnxVt7Or0vPtsjMrsqod8svy3HyBxE6EdjK8qaRKwYlt/v9hbj9hSJf4hnKXF5RpVldcVv/EFW/Zu7EFG/5ZZKyOnW4DGl2BhhbpSoog4MKzCrGsRp3im48Il0IPik4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754209048; c=relaxed/simple; bh=dG5Q14Vv2tG8ILJ0dE05rABknNd8Pl7HaZzDqnCNezo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NVcA2HZqsx1hkHvlsXfFchyqJw5vjrddyo8MLQbQPq+NzBUUih5T8VM/szrwBmintstFuYARkV4L8KaEB/7SCvyhVBbTY49YAKSUwQyIuaU2wiypK/o31ye2DZ7nIf+7Uk64qBk691qYFRLNNsUD0KUo1Iuy28Ol7VNILB8Xgp8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KmaIPYrn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KmaIPYrn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D895C4CEF8; Sun, 3 Aug 2025 08:17:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754209047; bh=dG5Q14Vv2tG8ILJ0dE05rABknNd8Pl7HaZzDqnCNezo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KmaIPYrn/8NwQLEGCvtM6+8llJX7vEXD820E83K7OaYX3+LF+MvRhDInEBUjAUF9l Nh3M9d3WwsKtr9oSZFqBuN2WPdAgnOV2J6VWT276fK3iHSSZYnyaObxp0G1JbAPMq2 bYwmUHrXdurSc0kqW2R4BZlFeC/EX0+o/F2hRaXAK97TUwsoFjJ9wMG1ckJEpwF4Xg Zlf3GTusnBKNloEvNJAFPVY9s44pLpRhy6OAQ0fEDUMAbDyCwWscksyTLw3psO1PRe sgfP1C+KN++ZvilYyPucuG0V5Ni3RiEBQWFOl6sNg9sR1uh6SaO2VAqeP/8BHrHCcP 20jsr6CI2zQSg== Message-ID: Date: Sun, 3 Aug 2025 10:17:21 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers To: Rob Herring , Laura Nao Cc: mturquette@baylibre.com, sboyd@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com, guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, =?UTF-8?Q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= References: <20250730105653.64910-1-laura.nao@collabora.com> <20250730105653.64910-10-laura.nao@collabora.com> <20250801135604.GA3045005-robh@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/08/2025 15:57, Rob Herring wrote: >> + reg: >> + maxItems: 1 >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + description: >> + Reset lines for PEXTP0/1 and UFS blocks. >> + >> + mediatek,hardware-voter: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function >> + MCU manages clock and power domain control across the AP and other >> + remote processors. By aggregating their votes, it ensures clocks are >> + safely enabled/disabled and power domains are active before register >> + access. > > I thought this was going away based on v2 discussion? Yes, I asked to drop it and do not include it in v3. There was also discussion clarifying review. I am really surprised that review meant nothing and code is still the same. Best regards, Krzysztof