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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RZrP3hCGwbIfXa03TRs9r5655C6bTGROrtypcSA5m3hd9QzsOzh9LAYydfpGKxMmBobiImfrNV6LWJhgSR8tS5yCbMKz/8tOgs18nqmL9dxs5DwI6X/vxiztZ/dyWp33CPUUbb+IwUJ+09hJ/xrwM9l3XT+FC936kwNayq/2KDBIm2WPQGAFltOuWrANFWiN7ZAYGLUcCea8+hGOGOj4lHX58fOL9nhIRfT0Tg69DD/NXKgBvbkkRay12DCUeKOzJPhDDzTSf2cxE8FxUW9AKmYyowqi3QSisfHGCjPOYFjcnGKvf+obQVj6WA08pIhvZ1L1oCEzr8jz9Hl9gw7fKwhRKeaPSnc3ywyHTUm8e1FOuj46u0kLZvl52zCk7dH6bLrC3XdAvOVsXwRPZks/DobJvXBDBXA4d/neEoaYCQH686dCh0v1SjycTSX409Wm X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2026 17:51:19.8232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc56deb4-8ac5-4a69-f052-08df29529682 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY6PEPF0000004B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8470 The Alternate Injection feature is a method to protect a SNP guest from malicious injection attacks. It allows the guest to control the interrupt injection. When this feature is enabled, interrupts are injected with the help of an agent called a Secure VM Service Module (SVSM) which executes in the security realm of the guest and uses Restricted Injection as the sole method to receive interrupts from the hypervisor. Add support for Alternate Injection. Signed-off-by: Melody Wang --- arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/boot/compressed/sev.c | 2 +- arch/x86/coco/core.c | 3 +++ arch/x86/coco/sev/core.c | 2 +- arch/x86/include/asm/msr-index.h | 4 ++-- include/linux/cc_platform.h | 8 ++++++++ tools/arch/x86/include/asm/msr-index.h | 4 ++-- 7 files changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a47a6beebfe3..52d627bb33f4 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -496,6 +496,20 @@ config AMD_SECURE_AVIC If you don't know what to do here, say N. +config AMD_ALTERNATE_INJ + bool "Support Alternate Injection" + depends on X86_X2APIC && AMD_MEM_ENCRYPT + help + Enable AMD Alternate Injection support for SNP guests. + + The Alternate Injection feature of SEV-SNP enhances the security of + a confidential VM by preventing the untrusted host from presenting + unexpected interrupts or exceptions, while still preserving the + standard interrupt dispatch semantics inherent to the x86 + architecture. + + If you don't know what to do here, say N. + config X86_POSTED_MSI bool "Enable MSI and MSI-x delivery by posted interrupts" depends on X86_64 && IRQ_REMAP diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index c6512f2ea31e..fc2029746c50 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -179,7 +179,7 @@ bool sev_es_check_ghcb_fault(unsigned long address) #define SNP_FEATURES_IMPL_REQ (MSR_AMD64_SNP_VTOM | \ MSR_AMD64_SNP_REFLECT_VC | \ MSR_AMD64_SNP_RESTRICTED_INJ | \ - MSR_AMD64_SNP_ALT_INJ | \ + MSR_AMD64_SNP_ALTERNATE_INJ | \ MSR_AMD64_SNP_DEBUG_SWAP | \ MSR_AMD64_SNP_VMPL_SSS | \ MSR_AMD64_SNP_SECURE_TSC | \ diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index 989ca9f72ba3..aabda3ddc0e2 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -107,6 +107,9 @@ static bool noinstr amd_cc_platform_has(enum cc_attr attr) case CC_ATTR_SNP_SECURE_AVIC: return sev_status & MSR_AMD64_SNP_SECURE_AVIC; + case CC_ATTR_SNP_ALTERNATE_INJECTION: + return sev_status & MSR_AMD64_SNP_ALTERNATE_INJ; + default: return false; } diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index eb2e853e950a..900a7ff8b639 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -78,7 +78,7 @@ static const char * const sev_status_feat_names[] = { [MSR_AMD64_SNP_VTOM_BIT] = "vTom", [MSR_AMD64_SNP_REFLECT_VC_BIT] = "ReflectVC", [MSR_AMD64_SNP_RESTRICTED_INJ_BIT] = "RI", - [MSR_AMD64_SNP_ALT_INJ_BIT] = "AI", + [MSR_AMD64_SNP_ALTERNATE_INJ_BIT] = "AI", [MSR_AMD64_SNP_DEBUG_SWAP_BIT] = "DebugSwap", [MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT] = "NoHostIBS", [MSR_AMD64_SNP_BTB_ISOLATION_BIT] = "BTBIsol", diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 82ca6356dc62..297c7dec795c 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -728,8 +728,8 @@ #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT) #define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5 #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT) -#define MSR_AMD64_SNP_ALT_INJ_BIT 6 -#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT) +#define MSR_AMD64_SNP_ALTERNATE_INJ_BIT 6 +#define MSR_AMD64_SNP_ALTERNATE_INJ BIT_ULL(MSR_AMD64_SNP_ALTERNATE_INJ_BIT) #define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7 #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT) #define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8 diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index 559353ad64ac..80d9f1de2ae8 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -104,6 +104,14 @@ enum cc_attr { * to run SEV-SNP guests with full Secure AVIC capabilities. */ CC_ATTR_SNP_SECURE_AVIC, + + /** + * @CC_ATTR_SNP_ALTERNATE_INJECTION: AMD Alternate Injection enabled. + * + * A Secure VM Service Module (SVSM) has started the guest with + * Alternate Injection enabled. + */ + CC_ATTR_SNP_ALTERNATE_INJECTION, }; #ifdef CONFIG_ARCH_HAS_CC_PLATFORM diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 18c4be75e927..e4eab2210518 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -721,8 +721,8 @@ #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT) #define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5 #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT) -#define MSR_AMD64_SNP_ALT_INJ_BIT 6 -#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT) +#define MSR_AMD64_SNP_ALTERNATE_INJ_BIT 6 +#define MSR_AMD64_SNP_ALTERNATE_INJ BIT_ULL(MSR_AMD64_SNP_ALTERNATE_INJ_BIT) #define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7 #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT) #define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8 -- 2.43.0