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Thu, 29 Oct 2026 03:57:16 -0700 (PDT) Received: from [10.217.217.199] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1a76037e2b5sm20562986c88.21.2026.10.29.03.57.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Oct 2026 03:57:16 -0700 (PDT) Message-ID: Date: Thu, 29 Oct 2026 16:27:08 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/12] dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock divider To: Krzysztof Kozlowski Cc: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Linus Walleij , Richard Cochran , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org References: <20261026-b4-pdm_clk_gp_mnd_v2-v2-0-ff8e4bc8d567@oss.qualcomm.com> <20261026-b4-pdm_clk_gp_mnd_v2-v2-1-ff8e4bc8d567@oss.qualcomm.com> <20261027-inescapable-rough-viper-6cd56d@quoll> Content-Language: en-US From: Taniya Das In-Reply-To: <20261027-inescapable-rough-viper-6cd56d@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI5MDA0MiBTYWx0ZWRfX94Cc7ikYkR8Z 8xJQD2j/Jx1Zqn1alq+9C9iun4jjKd/vCYG029JCdiAmQmhfvr6FrKzR1GcOofNNYdeMTsaYlD/ 1+/ZllU8aAPnYJy3TOiw2Ng+P/8YFtRb3QzyYJsZQhPZhOxzyJaSl/qLYvNOv1YIC1M4ed+iyXh Vs1xA5FjxvdcjGsEFHBSBiCHQxMAwVv5scVUw2VGKGS2QNDQ2Jv3xKvpGs7IBFyj0M51OSQhfY9 33TTjjz2Zj/LBOpjlNx2CC34k7kzMaQ5UqIR5Dl2Ub4NdUB+ZUqNkORAkGUPHLuU4632WT8Yg+r +XmdIgu+UataRsF2EVY7hi1g617/jfyyF3ehYH9ZT+a7E1Mrgfuy62qqjAR1tIr6lM9ghQQiT/S EnxETrPvpIi//owp2gu3dudkRGgVW9PSTcyQnfKdruRHuUOjTB/SPCW5Lu408iqCWz0f777dFhP 1Ndd7Ar2ei0BwxdnKMQ== X-Authority-Analysis: v=2.4 cv=E8tYNqdl c=1 sm=1 tr=0 ts=6ae3268e cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=LB2yG9bKkngd5w-dMicA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI5MDA0MiBTYWx0ZWRfX5NdCn7PS3pjq mFWKdO5S35DGAHjM4QKOnV1Zq/rGvyQsAEYTPuvejg9VYV3IVuX2GBLc+qDU/7hndecTfy2i4Sx uP7K1wufYG26OyxGk+Pfkx4SgA+sUsc= X-Proofpoint-ORIG-GUID: Wccu9x16bNqzYakQU-dnxZLOEXJ1Jjfg X-Proofpoint-GUID: Wccu9x16bNqzYakQU-dnxZLOEXJ1Jjfg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-29_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610290042 On 10/28/2026 12:17 AM, Krzysztof Kozlowski wrote: > On Mon, Oct 26, 2026 at 04:59:27PM +0530, Taniya Das wrote: >> Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN >> clock divider. The hardware generates a fractional output frequency >> from a fixed input clock (typically TCXO4) using the relation >> Fout = Fin * (M / N), with duty cycle controlled by a separate D >> register. The clock output is routed over a gpio controlled pin. >> >> Signed-off-by: Taniya Das >> --- >> .../devicetree/bindings/clock/qcom,clk-gp-mnd.yaml | 98 ++++++++++++++++++++++ >> 1 file changed, 98 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml b/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..8141f392c5d70acfc42cf1ff4b1722e1eff23afa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml > > Use fallback as filename, so qcom,sc7280-gp-mnd.yaml Sorry my bad, should have renamed it. > >> @@ -0,0 +1,98 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,clk-gp-mnd.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Peripheral Web's PDM GP_MN Clock Divider >> + >> +maintainers: >> + - Taniya Das >> + >> +description: | >> + The Peripheral Web's PDM GP_MN clock divider receives an input clock >> + (TCXO4) with frequency Fin and generates an output clock with >> + frequency Fout = Fin * (M / N) and a duty cycle controlled by D >> + and routed over a gpio pin. >> + >> + The divider is configured using three registers: >> + >> + - GP_MN_CLK_MDIV: holds the M value. >> + - GP_MN_CLK_NDIV: holds the ones complement of (N - M). >> + - GP_MN_CLK_DUTY: holds the D value. >> + >> + For every N input clock cycles the GP_MN produces M output clock >> + cycles. D is the number of native clock cycles in which the GP_MN >> + output is low, counted over 2^13 native clock cycles. >> + >> + Hardware constraints: >> + >> + M <= 511 >> + N <= 8191 >> + N > 2 * M >> + M < D < (N - M) >> + M and N must be coprime (no common divisor) >> + >> +properties: >> + compatible: >> + oneOf: >> + - const: qcom,sc7280-gp-mnd >> + - items: >> + - enum: >> + - qcom,sa8775p-gp-mnd >> + - qcom,qcs8300-gp-mnd >> + - qcom,qcs615-gp-mnd >> + - const: qcom,sc7280-gp-mnd >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: PDM XO4 source clock >> + - description: PDM AHB bus clock for register access >> + >> + clock-names: >> + items: >> + - const: pdm_clk > > pdm > >> + - const: ahb_clk > > ahb > will drop _clk suffix. >> + >> + '#clock-cells': >> + const: 0 >> + >> + assigned-clocks: >> + maxItems: 1 >> + description: Parent clock phandle used to set the input frequency. >> + >> + assigned-clock-rates: >> + maxItems: 1 >> + description: | >> + Rate for the parent clock in Hz. >> + Supported rates: 19200000, 9600000, 6400000, 4800000. > > Neither assigned-clocks nor assigned-clock-rates should be needed. > Parent clock is outside of scope of this binding. > Sure I will remove, but the parent clock input is a requirement of the Hardware and the output of this module entirely depends on the above ranges of frequencies mentioned and that is the reason to keep the rates specifically. I will capture it in the description and hope that should be fine. > >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - assigned-clocks >> + - assigned-clock-rates > > And these two should not be required, either. Will remove. -- Thanks, Taniya Das