From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF30C00449 for ; Fri, 5 Oct 2018 16:18:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 972F7214C2 for ; Fri, 5 Oct 2018 16:18:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 972F7214C2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730436AbeJEXSL (ORCPT ); Fri, 5 Oct 2018 19:18:11 -0400 Received: from mga02.intel.com ([134.134.136.20]:40260 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728967AbeJEXSK (ORCPT ); Fri, 5 Oct 2018 19:18:10 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Oct 2018 09:18:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,345,1534834800"; d="scan'208";a="86033243" Received: from 2b52.sc.intel.com ([143.183.136.147]) by FMSMGA003.fm.intel.com with ESMTP; 05 Oct 2018 09:18:23 -0700 Message-ID: Subject: Re: [RFC PATCH v4 3/9] x86/cet/ibt: Add IBT legacy code bitmap allocation function From: Yu-cheng Yu To: Eugene Syromiatnikov Cc: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue Date: Fri, 05 Oct 2018 09:13:40 -0700 In-Reply-To: <20181003195702.GF32759@asgard.redhat.com> References: <20180921150553.21016-1-yu-cheng.yu@intel.com> <20180921150553.21016-4-yu-cheng.yu@intel.com> <20181003195702.GF32759@asgard.redhat.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2018-10-03 at 21:57 +0200, Eugene Syromiatnikov wrote: > On Fri, Sep 21, 2018 at 08:05:47AM -0700, Yu-cheng Yu wrote: > > Indirect branch tracking provides an optional legacy code bitmap > > that indicates locations of non-IBT compatible code. When set, > > each bit in the bitmap represents a page in the linear address is > > legacy code. > > > > We allocate the bitmap only when the application requests it. > > Most applications do not need the bitmap. > > > > Signed-off-by: Yu-cheng Yu > > --- > > arch/x86/kernel/cet.c | 45 +++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > > > diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c > > index 6adfe795d692..a65d9745af08 100644 > > --- a/arch/x86/kernel/cet.c > > +++ b/arch/x86/kernel/cet.c > > @@ -314,3 +314,48 @@ void cet_disable_ibt(void) > > wrmsrl(MSR_IA32_U_CET, r); > > current->thread.cet.ibt_enabled = 0; > > } > > + > > +int cet_setup_ibt_bitmap(void) > > +{ > > + u64 r; > > + unsigned long bitmap; > > + unsigned long size; > > + > > + if (!cpu_feature_enabled(X86_FEATURE_IBT)) > > + return -EOPNOTSUPP; > > + > > + if (!current->thread.cet.ibt_bitmap_addr) { > > + /* > > + * Calculate size and put in thread header. > > + * may_expand_vm() needs this information. > > + */ > > + size = TASK_SIZE / PAGE_SIZE / BITS_PER_BYTE; > > TASK_SIZE_MAX is likely needed here, as an application can easily switch > between long an 32-bit protected mode. And then the case of a CPU that > doesn't support 5LPT. If we had calculated bitmap size from TASK_SIZE_MAX, all 32-bit apps would have failed the allocation for bitmap size > TASK_SIZE. Please see values below, which is printed from the current code. Yu-cheng x64: TASK_SIZE_MAX = 0000 7fff ffff f000 TASK_SIZE = 0000 7fff ffff f000 bitmap size = 0000 0000 ffff ffff x32: TASK_SIZE_MAX = 0000 7fff ffff f000 TASK_SIZE = 0000 0000 ffff e000 bitmap size = 0000 0000 0001 ffff