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[188.155.181.108]) by smtp.gmail.com with ESMTPSA id n10-20020a5d598a000000b001efab095615sm4434539wri.29.2022.02.28.01.54.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Feb 2022 01:54:23 -0800 (PST) Message-ID: Date: Mon, 28 Feb 2022 10:54:21 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 3/3] arm64: dts: rockchip: Add sata nodes to rk356x Content-Language: en-US To: Frank Wunderlich , "devicetree @ vger . kernel . org Damien Le Moal" , Rob Herring , Hans de Goede , Jens Axboe , linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org, Heiko Stuebner , Peter Geis , Michael Riesch , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Frank Wunderlich References: <20220227182800.275572-1-linux@fw-web.de> <20220227182800.275572-4-linux@fw-web.de> From: Krzysztof Kozlowski In-Reply-To: <20220227182800.275572-4-linux@fw-web.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/02/2022 19:28, Frank Wunderlich wrote: > From: Frank Wunderlich > > RK356x supports up to 3 sata controllers which were compatible with the > existing snps,dwc-ahci binding. > > Signed-off-by: Frank Wunderlich > --- > changes in v3: > - fix combphy error by moving sata0 to rk3568.dtsi > - remove clock-names and interrupt-names > changes in v2: > - added sata0 + 1, but have only tested sata2 > --- > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 +++++++++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 26 ++++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index 5b0f528d6818..2a2f65899d47 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -8,6 +8,19 @@ > / { > compatible = "rockchip,rk3568"; > > + sata0: sata@fc000000 { > + compatible = "snps,dwc-ahci"; > + reg = <0 0xfc000000 0 0x1000>; > + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, > + <&cru CLK_SATA0_RXOOB>; > + interrupts = ; > + phys = <&combphy0 PHY_TYPE_SATA>; > + phy-names = "sata-phy"; > + ports-implemented = <0x1>; > + power-domains = <&power RK3568_PD_PIPE>; > + status = "disabled"; > + }; > + > pipe_phy_grf0: syscon@fdc70000 { > compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > reg = <0x0 0xfdc70000 0x0 0x1000>; > @@ -114,3 +127,4 @@ power-domain@RK3568_PD_PIPE { > #power-domain-cells = <0>; > }; > }; > + No need for new line here, > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 7cdef800cb3c..484c5ace718a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -230,6 +230,32 @@ scmi_shmem: sram@0 { > }; > }; > > + sata1: sata@fc400000 { > + compatible = "snps,dwc-ahci"; > + reg = <0 0xfc400000 0 0x1000>; > + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, > + <&cru CLK_SATA1_RXOOB>; clock-names should be added. Also to bindings. Best regards, Krzysztof